sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<xypron> Is the cycle register meant to be available in the VS mode under KVM?
<xypron> GRUB tries to access it.
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<sorear> VS mode doesn't care that it's VS mode; the question is "is it meant to be available in S-mode as part of a BRS compliant initialization", which I don't think is stated anywhere but the safe answer is "yes"
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<xypron> sorear: thanks for confirming.
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