sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> isn't CYCLES supposed to require a call to BSI nowadays?
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<ganboing> CSR_CYCLE should always be readable from S, but the start/stop/clear are done through SBI call
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<xypron> Wouldn't a usable cycle register in a virtual CPU require KVM keeping track of when Linux schedules a vCPU on a hart and report the virtual cycle register according to the sum of cycles executed by vCPU while scheduled (and the counter not being inhibited).
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<conchuod> palmer: Can you pass this on to Charlie: "UBSAN: array-index-out-of-bounds in /stuff/linux/arch/riscv/kernel/vendor_extensions.c:41:15"
<conchuod> I dunno if it was already reported, kinda been outta the loop last few days.
<conchuod> I figure it is easy to reproduce if you have the vendor extensions stuff enabled, in my case the andes one.
* conchuod Ah, there was already a fix posted. Of course I find it /after/ I post about it and not before...
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<ja_02> Lol its always after
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<ganboing> @xypron exactly, and kvm already handles that by leveraging perf_event_create_kernel_counter(task=current).
<ganboing> When task != NULL, the event counters are per-task, so perf framework will handle the context switching
<xypron> ganboing: I have posted a GRUB patch to solve my issues with the cycle register: https://lists.gnu.org/archive/html/grub-devel/2024-08/msg00008.html
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