<Esmil>
la_mettrie: the register is used, just not through this macro definition directly. the driver uses the fact that the status registers are layed out one after another after STATUS0, and then calculates which bit in which register from the reset index
<mort>
change T to int and you see adding ints is 1 instr
<mort>
I don't know if this is clang's codegen missing a trick or if it has to be that way
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<cousteau>
maybe it was 2 and not 1
<cousteau>
in any case, yeah it seems that they didn't consider it common enough to add it to the base instruction set. I think the justification was that languages such as C don't use that sort of thing anyway.
<cousteau>
I think the B extension adds carry operations though
<jrtc27>
the three adds can be compressed
<jrtc27>
as can the ret
<jrtc27>
so it's not so awful
<mort>
hmm should clang have done that here or will the assembler take care of that
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<jrtc27>
compression is done by the assembler (though a smart compiler will choose instructions that are compressible where possible e.g. via register allocation heuristics)
<jrtc27>
if you enable Compile to binary you can see the disassembly along with the raw instruction bytes
<cousteau>
as in, choose registers that have a compressed instruction?
<jrtc27>
yes
<jrtc27>
and in some cases prefer one instruction sequence to another equivalent one because it can be compressed
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<muurkha>
mort: I was surprised by RISC-V's weak support for multiprecision math too, but consider that it trades off against simplicity for small implementations and performance for large ones
<muurkha>
and multi-precision math is definitely a lot less important for a 32-bit instruction set than it is for, say, an 8-bit instruction set
<mort>
if it's true that it can basically be written as 4 compressed expressions (with proper register allocation), then it won't be larger than two "proper" adc instructions; and if all compilers produce the same code for two-register adds, the big CPUs could probably macro-op fuse something
<mort>
so it kinda makes sense
<muurkha>
yeah. and mulh/mulhs/mulhu/mulhsu *is* present
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<conchuod>
btw palmer I see there's been nothing further on that canaan dt stuff you put on riscv-canaan_dt_schema, so I assume you can just take it /shrug
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