sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<arnd> conchuod: it always depends on the kind of patch: if you are doing the same obvious change across all architectures, a single patch is best. Same if you need to change the common code and architecture specific bits atomically to avoid build regressions in the middle of the series
<arnd> OTOH if you have changes that are nontrivial and need testing on a particular architecture, it's best to split it up
<arnd> as a rule of thuimb, I'd go with the contents of the changelog text: if you have multiple patches that can have the exact same description, that is a good indication that they should be combined. If a patch description mentions multiple independent changes in one patch, you should probably split it up
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<conordooley> arnd: Cool, thank you.
<conordooley> palmer: do you have anything queued for -rc3 fixes? I have a couple dt bits, but I won't bother sending a PR until next week if you have nothing.
<palmer> You can just send it
<palmer> I was going to look through stuff today anyway, there's probably something
<conordooley> I think you have some stuff from me that you postponed last week, so ye I think there is
<conordooley> I'll send when I get home so..
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<palmer> OK, no rush. I won't look until I get to the office, which will be a few hours
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<conchuod> Every time I think I have cleared the dtbs_check warnings, I get another.
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<drewfustini> Interesting news from Alibaba T-Head: "quad-core Xuantie C910 CPU up to 2.5GHz, 4 TOPs of NPU, 64-bit 4266MT on DDR, and a wide range of standard I/O interfaces." https://riscv.org/blog/2022/08/alibaba-cloud-unveils-chip-development-platform-to-support-developers-with-risc-v-based-high-performance-socs-alibaba-cloud/
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<conchuod> arnd: another one for you, sorry.. For touching all archs do I ignore all non-maintainer mails that get_maintainer spits out?
<arnd> conchuod: you should trim the Cc list to not have too many people on there, finding the right ones takes a little practice
<arnd> some people just show up because of previous cleanup commit, those can be left out
<conchuod> arnd: Aye, it;s still like 40 people + lists but I assume that;s normal
<palmer> IMO the most important bit are the lists, the folks who actually need to see each patch are on those lists anyway
<arnd> not necessarily, some of the lists have a lot of traffic
<arnd> there is a limit of 1024 characters for the Cc list
<palmer> so I guess my general strategy is to To the people who would merge the patch and have reviewed previous versions, To/CC the lists, and then not worry too much about the longer tail of getmaintainers suggests
<conchuod> for risc-v I know there's ~no point CCing Paul or Albert, but outside of here I have no idea
<palmer> ya, I guess it's kind of an art ;)
<arnd> if you are unsure, you could have one person and the list for each architecture
<conchuod> 139 words 1,672 characters
<conchuod> heh
<arnd> usually the main person comes first in get_maintainers.pl, or you can tell how many patches they authored in that list
<palmer> I've also found it useful to "git log --pretty=fuller" and see who's committing the patches to the files you're touching, they're generally a good person to make sure is To'd
<arnd> actually when you have a patch across architectures, you probably don't want the maintainers in To, as that should be the person to apply the patches
<conchuod> Aye, that'd be you.. Can I do lists in bcc?
<arnd> I would send a cross-architecture patch to:linux-arch@vger.kernel.org, Cc everyone else
<arnd> also me in To if you want me to apply the patch to the asm-generic tree
<conchuod> :+1: Ill work on cutting down the CC list so
<conchuod> 1008 chars, I guess that'll have to do. Thanks.
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<conchuod> Now to see if the world burns down (:
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