sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<dh`> offtopic question, but since nobody's talking anyway:
<dh`> anyone know if there was ever sparc hardware that actually implemented the relaxed memory model?
<dh`> I figure someone here might well have actual information :-)
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