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<MoeIcenowy>
drewfustini: plic does not define interrupt triggering type
<MoeIcenowy>
T-Head C906 defined some extra signal on synthesis time to judge whether a interrupt is edge or level
<drewfustini>
Ok, thank you for the explanation
<MoeIcenowy>
BTW on Allwinner D1, these signals on C906 is exposed as an extra register block on MMIO bus
<MoeIcenowy>
so that by setting up PLIC with these registers the interrupts could be set up as both types
<MoeIcenowy>
(but I think almost all peripherals on D1 is level triggered
<drewfustini>
My understanding is that the interrupt trigger type does not matter from the perspective of drivers/irqchip/irq-sifive-plic.c
<drewfustini>
Is that right?
<MoeIcenowy>
yes
<drewfustini>
thank you
<MoeIcenowy>
this source code file knows nothing
<MoeIcenowy>
how trigger type is decided is implementation-defined
<MoeIcenowy>
and D1 is another special situation that made some facility to allow runtime switch of trigger type
<MoeIcenowy>
(but considering PLIC is usually not directly exposed to external package, this seems to be not so necessary
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<drewfustini>
I'm working with a system where the PLIC implementation was translated from the Chisel implementation in Rocket Chip. The verilog shows that it is level-sensitive. It is good to know this does not matter for the irq-sifive-plic driver
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