sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<unlord> Hello
<unlord> I booted a fedora image using qemu-system-riscv64 and did not see support for the RVV instructions
<HdkR> I don't believe the kernel has upstream support for it currently?
<unlord> so even if I bought an Allwinner D1 SBC I couldn't program against them?
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<HdkR> Not sure on that one, downstream kernel could resolve that
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<courmisch> unlord: even if you bought that, it's implemented as draft version of the spec that is subtly and not so subtly incompatible with the ratified standard
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<unlord> courmisch: this is why I was asking if it was emulated somewhere?
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<HdkR> qemu and spike support it I believe. Just need some kernel tree somewhere that understands it :)
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<HdkR> (I'm also curious where a kernel tree exists to use it)
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<unlord> HdkR: huh, I didn't think qemu supported it
<HdkR> It's there in a relatively new version
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<unlord> I built from git, v7.0.0
<unlord> isa: rv64imafdcsuh
<unlord> oh, but my kernel is 5.5.0 from 2020
<HdkR> Yea, it exists in v7.0, just won't show up in /proc/cpuinfo if your kernel doesn't support it
<unlord> Well, now I get to solve two problems, time to build a gentoo image and kernel
<HdkR> But I don't even think latest upstream kernel supports it
<HdkR> Probably need some downstream thing
<unlord> Got a link?
<HdkR> I wish, I have no idea where that lives
<HdkR> I've been casually looking for it myself
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<HdkR> Time to sepnd a few days learning to pull kernel patches from lkml
<unlord> these are from nov last year, is this before the standard was ratified?
<HdkR> I don't know the ratification status
<HdkR> I was going to use the extension regardless
<unlord> I'd like to write some ASM against it
<HdkR> same
<unlord> is gas the best assembler to use?
<HdkR> I was going to JIT it, so not sure :)
<unlord> nice :)
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<smaeul> unlord: this is the latest version of the vector series (which still has some serious unresolved ABI concerns, but probably okay for testing): https://lore.kernel.org/linux-riscv/cover.1652257230.git.greentime.hu@sifive.com/
<smaeul> if you want to use vector extensions on D1, you need an assembler with RVV v0.7.1 support: https://github.com/riscv-collab/riscv-binutils-gdb/commits/rvv-0.7.1
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<unlord> smaeul: I don't own a D1, but I was hoping to do some testing on emulated RVV
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