sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<muurkha> hmm, does SeRV implement RV32E? does anything?
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<muurkha> apparently zephyr can be built to run on RV32E: https://docs.zephyrproject.org/latest/boards/riscv/index.html
<muurkha> but I think the only "board" in the list that is RV32E is QEMU?
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<MoeIcenowy> muurkha: I think PicoRV32 has E support
<MoeIcenowy> openE902 is E-only, no I option
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<drewfustini> Is RV32E ratified in the Unprivileged spec?
<jrtc27> no
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<muurkha> MoeIcenowy: thanks! I didn't know that about PicoRV32 or openE902
<muurkha> yeah, riscv-spec-20191213.pdf sha1 288477794169c2c2c728ba37c0f82caa187664b1 chapter 4 says it's a "draft proposal for the RV32E base integer instruction set", version 1.9, which I hadn't noticed. I thought it was final
<muurkha> thanks jrtc27!
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