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<conordooley>
It just so happened that I wanted to use that debugfs interface myself, seems like all that's missing to use it is for riscv to enable HARDIRQS_SW_RESEND /shrug
<conordooley>
idk if it does what youre looking for drewfustini but I CCed you on the patch anyway. GENERIC_IRQ_DEBUGFS has to be enabled too, but that's exposed
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<drewfustini>
conchuod: interesting, I had enabled IRQ debugfs and have been using it. For example, the supervisor external interrupt:
<drewfustini>
conchuod: I'm reading your email. Do you mean the retriggering could be controlled through debugfs?
<drewfustini>
Looking at the code, it seems like the main thing that HARDIRQS_SW_RESEND does is define irq_set_parent() and create a resend_tasklet
<drewfustini>
smaeul: unfortunately, the pending bits are read only in the PLIC implementation I'm using. It is essentially just a verilog translation of the sifive chisel for the PLIC. there were not any extra registers added by the RTL to artificially trigger a PLIC source.
<drewfustini>
My system I have SMP enabled in kernel config but bootloader is currently only enabling 1 Hart. I think this might be in a corner case as plic_set_affinity() seems to be the problem
<drewfustini>
I have noticed that none of the PLIC interrupt sources are ever enabled. In drivers/irqchip/irq-sifive-plic.c, there is plic_set_affinity() which has this line to unmask the interrupt sources that are configured to be active.
<drewfustini>
Line 154: plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
<drewfustini>
That third argument is "enabled" and !irqd_irq_masked(d) is always 0. My suspicion is that this may be due to the unusual circumstance of SMP enabled but only one hart being active.
<drewfustini>
I've been trying to figure out why my UART (linux interrupt 1) does not have the IRQD_ACTIVATED dstate flag.
<conchuod>
drewfustini: with that flag enabled you can do an "echo -n trigger > 9"
<conchuod>
I just get back -EINVAL without enabling HARDIRQS_SW_RESEND b/c the plic has no irq_set_irqchip_state() which the GICv3 etc has
<conchuod>
That echo -n trigger calls irq_inject_interrupt() -> check_irq_resend() -> irq_sw_resend() & irq_sw_resend() is gated by HARDIRQS_SW_RESEND
<drewfustini>
Ah ok, thanks for the explanation
<conchuod>
tbh, I never even tried to do a "cat 9" so I didn't know it had other functionality!
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<drewfustini>
Yes, I had seen maz talking about it with regards to /proc/interrupts not matter that much and people should be looking at /sys/kernel/irq and /sys/kernel/debug/irq
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