sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<conordooley> geertu what did you mean about the sort order?
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<geertu> whois conchuod
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<geertu> same as conordooley, right? ;-)
<geertu> conchuod: both spi and usb sort after soc
<geertu> conchuod: Is "microchip,mpfs-spi" only for hard SPI, or can it be instantiated in an FPGA, too?
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<conordooley> geertu sorry for the confusion, I have two instances connected
<conordooley> So both are me (and on the same IRC account)
<conordooley> And yeah, both sort after SoC but the order of the resolution matters
<conordooley> re: spi, for 90% of the "hard" peripherals the registers are the same as the "soft" IP
<conordooley> So the qspi & the i2c can fall back to the IP core compatible, but not for spi.
<conordooley> The bits in the registers are the same (or the hard one has more), but the addresses are not.
<conordooley> Hopefully I'll have a patch to "fix" that soon, but been out of work so no access to a protocol analyser or FPGA programmer haha
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<Esmil> smaeul: yeah, i think something might be up with the cache management in the d1-wip branch. now i switched to a root filesystem on a usb stick, and it happens less, but it still reads wrong data once in a while
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<conchuod> Esmil: You're Emil right?
<conchuod> If someone was telling me "x works fine on VisionFive, but not anything else" what defconfig are they likely to be using?
<conchuod> IOW, what is the defconfig for the default kernel
<Esmil> conchuod: Uhm.. the default visionfive branch of github.com/starfive-tech/linux comes with a visionfive_defconfig
<conchuod> of course :facepalmL
<Esmil> But it's optimised for ease of testing the latest kernel, so really minimal and no modules
<conchuod> Basically I got a report (why me????) that hwloc is broken on sifive stuff and working on the starfive
<conchuod> It reports the harts as threads of the same core not as cores
<Esmil> oh, interesting
<conchuod> /sys/devices/system/cpu/cpu0/topology
<Esmil> Ah, Jonas Hahnfeld recently added the cpu-map node to the device tree. I don't think any other risc-v board has that
<conchuod> what do you get for physical_package_id or core_id
<conchuod> Ahh, so what you're saying is that the /downstream/ dt has that?
<Esmil> yes
<conchuod> I guess I should cherry pick his patch and "fix" the other dts then...
<conchuod> cpu-map has existed for years - why aren't we using that at the moment? palmer any idea?
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<conchuod> I was looking at Documentation/devicetree/bindings/cpu/cpu-topology.txt earlier and the fu500 is one of the examples lol
<Esmil> conchuod: it's not in a separate patch in starfive-tech/linux, but you can probably find it from here: https://github.com/starfive-tech/linux/pull/58
<Esmil> yes, but not in the actualy device tree heh
<conchuod> Seems like that should be fixed to me /shrug
<conchuod> I'll send the patches and leave it up to others to decide
<Esmil> *thumbs up* if you send a patch for the upstream jh7100.dtsi please name the labels U74_0 and U74_1 like in starfive-tech/linux
<conchuod> Yeah, I'll just lift the pactch from there.
<conchuod> I'll do one for them all I guess.
<Esmil> yeah, unfortunately it's not a separate patch in starfive-tech/linux
<Esmil> that's why i linked the pull request
<conchuod> I dont get you
<conchuod> A commit is a patch?
<Esmil> yes, but it has been squashed into the commit adding all the other non-upstream changes to the device tree
<conchuod> gah and he deleted the branch from his repo
<Esmil> conchuod: http://sprunge.us/dozaG8
<conchuod> You all make me seem so lazy here
<conchuod> thanks
<Esmil> just remember the labels ;)
<conchuod> I'll get them wrong, just for you
<conchuod> For this sort of thing, I never know - do I need to make you "Co-developed-by"?
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<kettenis> I need to submit a fixed version of that
<conchuod> I was just about to say ;)
<conchuod> I noticed another typo, it's "correct"
<Esmil> kettenis: yes please. i put it in starfive-tech/linux, but upstream would be better
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<conchuod> What's your email for SoB Esmil? Emil Renner Berthing <emil.renner.berthing@canonical.com> ?
<kettenis> Esmil: I was wondering whether it removes the need for the interrupt workaround in the cache controller
<conchuod> (since the label swap was done by you downstream)
<Esmil> kettenis: i tried, but unfortunately it doesn't seem so
<Esmil> conchuod: yes, that's fine. actually kernel@esmil.dk would be more correct since i did that just before i started at canonical
<conchuod> You doing risc-v there?
<Esmil> yes
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<conchuod> Cool :)
<conchuod> And ye, esmil.dk "feels" more correct to me too.
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<conchuod> There's a couple of you guys then Esmil? Heinrich & Alex are doing risc-v stuff too right?
<Esmil> yes
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<conchuod> Esmil: part of me hates the U74_# since all the rest are cpu# haha
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<Esmil> yeah, I just don't want to change it in case someone needs a reference to the 32bit core on the SoC
<Esmil> ..and labeling by the type of core seems to be the pattern used by ARM boards with multiple cores
<conchuod> The 32 bit core?
<conchuod> There's only u74s in the dt?
<Esmil> yes, for now
<conchuod> Why not just add the 32 bit one as disabled?
<conchuod> Would match the sifive{,-based} stuff
<Esmil> yeah, i probably should have, but when I sent in the upstream dt it only contained the peripherals that is actually usable by upstream right now.
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<conchuod> It's "your" dt & not usable by Linux so idc :)
<Esmil> oh you mean in the starfive-tech/linux tree
<conchuod> No, upstream.
<conchuod> If it's not "yours" then I dunno whose it is!
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