<Esmil>
smaeul: yeah, i think something might be up with the cache management in the d1-wip branch. now i switched to a root filesystem on a usb stick, and it happens less, but it still reads wrong data once in a while
crabbedhaloablut has quit [Ping timeout: 268 seconds]
cousteau has quit [Remote host closed the connection]
cousteau has joined #riscv
memoryleak has quit [Ping timeout: 246 seconds]
memoryleak has joined #riscv
aerkiaga has joined #riscv
loki_val has quit [Remote host closed the connection]
crabbedhaloablut has joined #riscv
tsraoien has joined #riscv
aerkiaga has quit [Remote host closed the connection]
mthall has quit [Read error: Connection reset by peer]
mthall has joined #riscv
BootLayer has quit [Quit: Leaving]
radu242 has joined #riscv
tsraoien has quit [Ping timeout: 244 seconds]
lagash has quit [Ping timeout: 240 seconds]
erg_ has joined #riscv
dor has quit [Ping timeout: 256 seconds]
ssb has quit [Ping timeout: 256 seconds]
ssb has joined #riscv
gorgonical has joined #riscv
EchelonX has joined #riscv
BootLayer has joined #riscv
lagash has joined #riscv
Andre_H has joined #riscv
erg__ has joined #riscv
erg_ has quit [Ping timeout: 276 seconds]
erg_ has joined #riscv
erg__ has quit [Ping timeout: 240 seconds]
cousteau has quit [Quit: ♫ I can't forget the day I shot that network down ♫]
<kettenis>
I need to submit a fixed version of that
<conchuod>
I was just about to say ;)
<conchuod>
I noticed another typo, it's "correct"
<Esmil>
kettenis: yes please. i put it in starfive-tech/linux, but upstream would be better
erg__ has joined #riscv
<conchuod>
What's your email for SoB Esmil? Emil Renner Berthing <emil.renner.berthing@canonical.com> ?
<kettenis>
Esmil: I was wondering whether it removes the need for the interrupt workaround in the cache controller
<conchuod>
(since the label swap was done by you downstream)
<Esmil>
kettenis: i tried, but unfortunately it doesn't seem so
<Esmil>
conchuod: yes, that's fine. actually kernel@esmil.dk would be more correct since i did that just before i started at canonical
<conchuod>
You doing risc-v there?
<Esmil>
yes
erg_ has quit [Ping timeout: 276 seconds]
<conchuod>
Cool :)
<conchuod>
And ye, esmil.dk "feels" more correct to me too.
erg_ has joined #riscv
erg__ has quit [Ping timeout: 244 seconds]
Narrat has joined #riscv
<conchuod>
There's a couple of you guys then Esmil? Heinrich & Alex are doing risc-v stuff too right?
<Esmil>
yes
erg_ has quit [Ping timeout: 276 seconds]
davidlt has joined #riscv
<conchuod>
Esmil: part of me hates the U74_# since all the rest are cpu# haha
BootLayer has quit [Quit: Leaving]
<Esmil>
yeah, I just don't want to change it in case someone needs a reference to the 32bit core on the SoC
<Esmil>
..and labeling by the type of core seems to be the pattern used by ARM boards with multiple cores
<conchuod>
The 32 bit core?
<conchuod>
There's only u74s in the dt?
<Esmil>
yes, for now
<conchuod>
Why not just add the 32 bit one as disabled?
<conchuod>
Would match the sifive{,-based} stuff
<Esmil>
yeah, i probably should have, but when I sent in the upstream dt it only contained the peripherals that is actually usable by upstream right now.
aerkiaga has joined #riscv
<conchuod>
It's "your" dt & not usable by Linux so idc :)
<Esmil>
oh you mean in the starfive-tech/linux tree
<conchuod>
No, upstream.
<conchuod>
If it's not "yours" then I dunno whose it is!