sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<palmer> mmind00: looks like it's a QEMU regression
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<conchuod> palmer: you figured out b4 yet?
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<conchuod> Reading the risc-v mailing lists is awful, everything is formatted differently :puke:
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<conchuod> Esmil: do I need to do anything specific to replace the u-boot on my V5 beyond wrapping with opensbi?
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