sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<drewfustini> has anyone ever encountered no plic being listed in /proc/interrupts but kernel log does indicate plic driver loaded ok?
<drewfustini> "[ 0.000000] plic: interrupt-controller@10000000: mapped 31 interrupts with 1 handlers for 2 contexts."
<drewfustini> the corresponding node:
<drewfustini> plic0: interrupt-controller@10000000 {
<drewfustini> reg = <0 0x10000000 0 0x2000000>;
<drewfustini> compatible = "sifive,plic-1.0.0";
<drewfustini> #interrupt-cells = <1>;
<drewfustini> riscv,ndev = <31>;
<drewfustini> interrupt-controller;
<drewfustini> interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
<drewfustini> };
<drewfustini> Setting aside SoC specific aspects, anyone have suggestions as to where to look to understand why the plic doesn't show up at all in /proc/interrupts ?
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<conchuod> drewfustini: do you not see it as the parent for the various interrupts in /proc/interrupts?
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<conchuod> Or is it that you expect to see an entry for it itself?
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<conchuod> I have such bad luck with buying boards recently.. My visionfive order became a radxa zero & my Beaglebone AI64 was "delivered" but not to me :/
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<drewfustini> conchuod: nothing with the plic in /proc/interrupts, just the riscv intc
<drewfustini> I am thinking that maybe this means the serial driver is not requesting the interrupt from the plic correctly
<drewfustini> I suppose the plic could be registered okay and just not show up as there is nothing successfully using an of the plic interrupts
<drewfustini> I think I probably need to trace what 8250_dw.c is doing with regards to registering the interrupt
<drewfustini> conchuod: regarding BBAI64, shoot me an email and I'll see if we can get one for you drew@beagleboard.org
<conchuod> Hah, thanks Drew. Hopefully DigiKey can figure out where the one I bought went...
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<conchuod> Hmm drewfustini out of curiosity, what driver has been bound to that dt entry?
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<la_mettrie> in the file jh7100.dts ethernet has two values in interrupts while its interrupt node (plic) has #interrupt-cells = <1> ...is this normal?
<la_mettrie> *jh7100.dtsi
<conchuod> la_mettrie: interrupts cells means cells per <>, not a limitation on how many interrupts it can have
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<conchuod> So the 6 & 7 there means both interrupt 6 & 7 are from the gmac, but each interrupt is described by one cell/attribute
<la_mettrie> okay, danke
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<conchuod> palmer: just to make sure, you've just not had a chance to merge my pr yet - as opposed to it's gone AWOL w/ email shittery
<palmer> sorry, I didn't know there was a PR
<palmer> I'm still trying to sort out this QEMU/OpenSBI update
<palmer> it's making all my tests fail, which is a huge PITA
<palmer> you're talking about "[GIT PULL] Microchip devicetree fixes for 5.19-rc6"?
<conchuod> Yup, that's the one!
<palmer> OK
<palmer> I just put it it staging, it'l probably fine
<palmer> sorry I missed it, probably best to just ping if you have a PR for now
<palmer> at least until I get un-buried...
<conchuod> Ye, that's nw. I assume you did get the email then & just didn't get a chance to look?
<palmer> yep
<palmer> sorry, didn't get to the email
<palmer> if I'd seen it I would have merged it
<palmer> I'm just a few thousand emails deep right now
<conchuod> That's fine. I just knew before you had issues getting mail from me so wanted to make sure...
<palmer> ya, also a good reason to poke IRC
<palmer> I intend on merging PRs fast, as there should be no question about stuff being reviewed at that point
<conchuod> I'll have another one later this week b/c it seems we're about a week or so out from the mw. I'll put lore links to the reviewed-or-tested-but-not-microchip devicetrees in the cover rather than bump given your mail volume!
<palmer> you can also just ping them here, if you think they're ready to go
<palmer> that's probably faster ;)
<conchuod> Prepare for wall of text so haha
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<palmer> NP
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<davidlt> conchuod, are you Conor D.?
<conchuod> Dooley? Yes
<conchuod> Conchubhar is my name in our other national language ;)
<davidlt> conchuod, your email constantly fail DMARC and thus are sent to spam folder. I guess that could be a problem.
<davidlt> I have seen that you are trying to sort that out with your IT.
<conchuod> Yeah, supposedly that is fixed as of yesterday.
<davidlt> I just see another email (7 minutes ago) which went to spam.
<conchuod> At least, we have DKIM c=relaxed/simple now rather than simple/simple
<davidlt> DMARC:'FAIL'
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<palmer> FWIW, I also get the "^M" that usually means Outlook is involved, which is generally a endless pit of headaches
<conchuod> For god's sake
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<davidlt> conchuod, I see: "arc=fail (body hash mismatch);"
<conchuod> Hmm, I don't see any issues in my other email
<davidlt> SPF and DKIM pass
<davidlt> conchuod, funny thing is that not all your emails fail, I would say it's 50/50.
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<conchuod> Are you talking about my one to Andy just now?
<davidlt> conchuod, yes, that's one failed
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<conchuod> arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com);
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<conchuod> That's what I got on it in my non-microchip account. It's google workspaces so I assume the same as rivos
<conchuod> Exchange makes my eyes bleed sometimes palmer
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<davidlt> My gmail says it's a fail ;) Well, I am not a full email guru so not sure what's happening.
<conchuod> hmm, I actually see the body hash mismatches on other emails though. I wonder if it depends which mailing list actually does the bounce.
<conchuod> Did you get it from the riscv list?
<palmer> conchuod: I have a "Received: from CO1PR11MB5154.namprd11.prod.outlook.com" in the PR email, which has the ^M from Outlook (though it ended up in my inbox)
<davidlt> arc=fail (body hash mismatch); dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=microchip.com
<conchuod> I think you'll likely be fine Palmer b/c youre in the to/cc so you're not getting affected by the bouncing via mailing lists.
<palmer> ya, I think so
<palmer> all those pass for me, but it probably skipped LMKL
<conchuod> I suspect that david got it from infradead and that's the problem.
<palmer> yep
<davidlt> Yeah, I get things via mailing list.
<conchuod> the lkml/vger bounces are fine (how I got the Andy one that passes)
<palmer> that was always the issue with the @google.com DMARC stuff, it even depended on which list you got the mail from
<conchuod> but infradead ones are not, those get arc=fail for me
<davidlt> conchuod, I actually check spam folder more regularly now just to see if there any new patches from you :)
<conchuod> idk what I am meant to do if it is a infradead-only problem? Maybe talk to dwoodhouse haha
<conchuod> davidlt: save yourself the mouse clicks and just do "if from:conor.dooley@microchip.com then: never mark as spam" in a filter I guess
<palmer> conchuod: I think asking David is the best way to go, but IIRC we could never sort out the Google issue
<palmer> another option is to just send from a different address (kernel.org, gmail, whatever) -- if corp folks want @microchip.com in the patches then just commit them that way, git will add a second "From:" header
<conchuod> Yeah, I do the From: @mchp anyway on stuff I send from home. Got that okayed :)
<conchuod> format patch/send email do it for yah
<conchuod> And I dunno if you wanna wait for v5.21 for this one b/c it is missing DRM taking the first two binding conversions:
<conchuod> None of the SiFive stuff has got a comment on any version so yeah /shrug
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<palmer> OK, I'll take a look at those
<palmer> I think I'm back to a stable enough setup that I can actually merge stuff...
<conchuod> :+1: thanks
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<gorgonical> experiencing a pagefault during memset of a region 0xffffffd8000ddfff, counting down from 0xffffffd8000dfd3c to 0xffffffd8000dd000. However, qemu's `info mem` shows this: ffffffd800000000 0000000080200000 0000000007e00000
<gorgonical> Could this be a TLB issue?
<gorgonical> and i can poke the memory with gdb just fine
<gorgonical> I'm asking here cause this is on riscv and wonder if this behavior could be riscv specific
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