sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<muurkha> I got my first RISC-V chips yesterday! Also my first FPGA devboard
<muurkha> a Longan Nano, an ESP32-C3 devboard (which Digi-Key shipped me with a burned-out red part of the RGB LED but meh), and three more ESP32-C3s
<muurkha> davidlt: what was the change in the definition of RV64GC?)
<muurkha> did CSRR get moved out of the base I ISA into the Zicsr extension?
<jrtc27> yes but G includes Zicsr
<muurkha> thanks jrtc27! so does that mean G(C) *didn't* change?
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<jrtc27> yes
<muurkha> thanks!
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<solrize> muurkha, where was the nano shipped from if you happened to notice? have you done anything with it yet, or anyway opened up and looked at it? any impressions?
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