sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<palmer> smaeul: is Heiko in here right now? the obvious handles aren't tab-completing
<smaeul> mmind00 ^
<palmer> I'm trying to sort out what to do with this D1 patch set: it's still failing to boot for me, and given how late it is in the merge window I think it's probably done unless I'm screwing something simple up
<smaeul> the cover letter even suggests waiting until after the merge window, so I don't think anyone will have a problem with that
<smaeul> the series works for me, but I've only tried it on real D1 hardware
<palmer> mmind00: just LMK, I'm testing a merge of my riscv-d1 branch (f705a2550d38 - (palmer/riscv-d1) riscv: add memo) into for-next, but I don't see how that'd be different
<palmer> smaeul: I thought it read like he wanted it for this MW? let me look...
<palmer> ya, I guess "this series should be merge after that" probably means "after the merge window" -- I thought he was saying "after the ISA extension series"
<palmer> mmind00: I'm going to wander off, but this pokes my phone (which sometimes works) -- feel free to yell if you were looking for these in this MW and there's something simple, I'll just be drinking ;)
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<palmer> atishp[m][m]: so even in the flock'd setup, I'm getting some pre-boot-spew errors. It's -smp 32 / NR_CPU=4, though, so maybe it's what you were seeing? this is defconfig and Alistar's queue
<atishp[m][m]> Do you have CONFIG_RISCV_BOOT_SPINWAIT disabled ?
<atishp[m][m]> I did not see anything related to that in your CI repo.
<atishp[m][m]> palmer: ^^
<atishp[m][m]> btw..I was able to run all your configs serially without any issue
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<palmer> OK, I have spinwait=y
<palmer> so that one's just an old issue, let me try to dig through some more...
<palmer> shouldn't spinwait depend on sbi-0.1?
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<atishp[m][m]> spinwait=y may fail for NR_CPU < -smp cases depending on the boot hartid
<atishp[m][m]> <palmer> "shouldn't spinwait depend on sbi..." <- ideally yes and it should depend on M_MODE
<atishp[m][m]> But I was not sure if I will be breaking somebody's build. So I did not. We can do it now because we have disabled SBI v01 now anyways
<palmer> atishp[m][m]: IIRC sbi-0.1 systems use spinwait, or am I misunderstanding the feature?
<atishp[m][m]> yes. but not the other way around. spinwait will also work for SBI v0.2 but you can't run configs like NR_CPU < -smp or discontinuous harts
<atishp[m][m]> so everybody should just move away spinwait
<palmer> I'll write up a patch
<atishp[m][m]> thanks
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<palmer> atishp[m][m]: palmer/riscv-spinwait
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<jrtc27> you can do spinwait just not how it's currently done
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<gordonDrogon> well, I appear to habr bludgeoned the NeoRV32 cre into the Gowin/tang 9K core and it even appears to work.
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<muurkha> fabulous, congratulations
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