kaph_ has quit [Read error: Connection reset by peer]
repnop has joined #riscv
<repnop>
heya folks, I'm looking to implement thread local storage for a project of mine, and I'm a little confused on how it works. referencing the psABI doc, its not clear to me how things are set up, mainly the size and layout of the main TLS Variant I data structure specified in Drepper's paper. is the TCB total size equal to `TLS_DTV_OFFSET` and the thread local section data copied after it? if so, then the `dtv_t,1` is just equal to `tp`, right? I don't
<repnop>
intend to have dynamic library loading, so I'm just dealing with individual PIEs that have their own TLS. also if anyone has any resources which explain this stuff a bit easier, it'd be much appreciated!
freakazoid333 has quit [Ping timeout: 260 seconds]
<gordonDrogon>
solrize, Allwinner D1 SoC ... I've seen a couple with that SoC now - seems to be some controversy around it but I guess that's what's going to happen when bigcorp uses some open core - they'll adapt it to their own uses.
freakazoid333 has joined #riscv
jwillikers has joined #riscv
jwillikers has quit [Remote host closed the connection]
<solrize>
gordonDrogon, you mean there's undocumented system stuff? hmm yeah that is typical
<gordonDrogon>
solrize, that plus I think I read that they'd added in some of their own opcodes..
<gordonDrogon>
trying to work my way round the esp32-c3 stuff too - there is a hardware reference manual, but it's short on one or 2 details, but maybe that's not so important for me right now anyway.
<solrize>
c3 also has closed wireless stack i expect
<solrize>
allwinner would also ofc
<gordonDrogon>
so still on the ultimate quest for a nice SoC that I can boot my own code from power on .. one day!
<gordonDrogon>
the other thing is to support a usb keyboard- that seems non-trivial. there is a gowin modue for it in their cores, but no documentation )-:
<solrize>
i think there are some POWER chipsets where you can program everything
jmdaemon has joined #riscv
<gordonDrogon>
yea, a lot of the ones from the old days - early sparc, i860, 68K, transputer and so on ..
<smaeul>
if you allow for a first-stage bootloader baked into the SoC as a true ROM, D1 and several ARM-based SoCs already meet that requirement
<gordonDrogon>
oh ARM would be trivial - almost too easy - but for many reasons I don't want to use ARM - this is purely a personal/hobby project although there may be a tiny/niche market for it, but no ARM for now.
<gordonDrogon>
e.g. if I wanted to go ARM, I'd just use a Pi Zero and one of the many baremetal frameworks for it, but where is the fun in that ;-)
<smaeul>
POWER doesn't have that limitation because it has reprogrammable flash _inside the SoC_ for the first stage
<smaeul>
(and that flash can be recovered from an external interface)
<gordonDrogon>
I can get what I want in an FPGA, but I'm finding the learning curve to be somwhat vertical right now ... 45 years of "traditional software + hardware with nothing more than a GAL, now head-first into FPGAs... eek!
derelict has quit [Quit: bye]
geranim0 has joined #riscv
<q66>
<smaeul> if you allow for a first-stage bootloader baked into the SoC as a true ROM, D1 and several ARM-based SoCs already meet that requirement
<q66>
i'd say most common arm socs have that, no?
derelict has joined #riscv
<q66>
it's nice not to have to worry about the possibility of bricking your device
<smaeul>
some SoCs still have a DRAM init blob (i.MX8) or a PHY matrix blob (layerscape) or a GPU init blob (RPi)
<smaeul>
and I assume qcom requires some blobs, so I don't know if "most common" ARM SoCs can boot with just your own code (+ built-in ROM)
<q66>
ah, fair enough
<gordonDrogon>
The esp32-c3 has a rom baked-in - I did think I had bricked it a couple of days ago but I fixed it by having to manually set some flash parameter in the openFPGAloader command...