sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<conordooley> geertu: was talking a look at how you had done the reset controller for the cpg-mssr/rzg2l, seems fairly straightforward? I assumed that it'd be more tightly coupled to the individual clocks, but follows a "different feature in the same driver" kind of format?
<conordooley> as in, the dt entirely determines the link between peripherals and their reset, rather than (since the reset and clocks have the same index) the reset being part of the clock
<conordooley> clock struct*
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<geertu> conordooley: Yes, on Renesas R-Car SoCs, there is a one-to-one mapping for clocks and resets
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<josuah> renesas? renesas did a risc-v?
<josuah> ah that is right: RZ/Five. Nice!
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<conordooley> unfortunately I don't have a 1:1 mapping, but I would like to use the same indexes as the clocks. I do have a reserved clock/reset, so I guess I need an xlate anyway to account for that & could just account for the offset of 3 there
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