sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<gordonDrogon> given up with the Tang nano 9k FPGA for now - it's a bit too much for my brain to cope with - steep learning curve, however I did get the neorv32 core running at 54Mhz inside it with some of my own code, so that's something.
<gordonDrogon> moved onto the esp32-c3 boards I now have - these seem ok and will be better once I've freed myself of the shackles of the grossness that is arduino ...
<gordonDrogon> https://github.com/cpq/mdk looks to be a very good start.
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<Jmabsd> Guys are any interesting high performance RISCV processors on the way now
<Jmabsd> By the way SiFive need to open source their base processor and firmware, that is an unhealthy proprietary game to promise that those will *never* be open
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<Jmabsd> drmpeg: yeah. how close to buyable is it?
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<drmpeg> If I have a board by Christmas, I'll be happy.
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<mort> weren't there some unfortunate news about sifive some time ago
<mort> can't recall what they were
<lagash> Intel deal?
<mort> oh right, the deal for intel to buy them
<mort> did that fall through
<gordonDrogon> well, someone in the ESP32-C3 team has a sense of humour: Guru Meditation Error: Core 0 panic'ed (Environment call from M-mode)
<gordonDrogon> it also seems the ROM in these things actually gives out sensible data too - like the value of the PC, so I can see what it tripped up on - an ecall instruction, so that's hardly surprising, however I'd have hoped my code might have printed 'stuff' before then... but still.
<lagash> Fall through? It failed didn't it?
<gordonDrogon> it failed - yes - but I have code before the ecall to print stuff out via the on-board uart - that code hasn't worked.
<gordonDrogon> the uart works ok from C - I'm trying to make it work from ASM.
<gordonDrogon> oh well that's intersting. writing a byte to the UART needs SW and not SB ... So it lives!
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<gordonDrogon> BCPL: Hello, world!
<gordonDrogon> and I'm happy as I've booted my BCPL OS on some real RISC-V hardware.
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<gordonDrogon> got to write a filing system now.
<Jmabsd> > oh right, the deal for intel to buy them
<Jmabsd> mort: i hope it failed!
<LxGHTNxNG> Intel and AMD need to be broken up.
<Jmabsd> drmpeg: who manufactures Horse Creek, Intel??
<Jmabsd> what lithography?
<Jmabsd> LxGHTNxNG: Intel is not a very attractive business. They are not doing very well.
<Jmabsd> They do have the fastest processors per EUR is it (does Power10 beat Xeon)
<Jmabsd> but Intel are truly slow, and their arch is proprietary so they are naturally out-competed by RISCV and ARM.
<Jmabsd> however the AMD64+Windows movement indeed is huge
<LxGHTNxNG> ARM is also proprietary, but with less discriminatory licencing-out.
<Jmabsd> Well Intel has essentially no licensing heh.
<Jmabsd> The Intel+AMD+VIA pact ...
<LxGHTNxNG> now just intel and amd, as via isn't anymore
<Jmabsd> archaic
<LxGHTNxNG> I've heard that IBM, the primus inter pares of OpenPOWER, is somewhat floundering also
<Jmabsd> describe, floundering
<LxGHTNxNG> excessively split corporate personality
<Jmabsd> LxGHTNxNG: oh interesting. like what? a well paid PHP script kiddies department who think they could ever, every accomplish anything but who have astronomic self entitlement and arrogance? :)
<Jmabsd> i heard they fired their older staff en masse, that does sound like a mistake, to strictly discriminate based on age.
<Jmabsd> their age threshold for "old" was not high, 47 or something? sounded like epic mistake.
<LxGHTNxNG> I've never worked at IBM so I wouldn't know
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<LxGHTNxNG> I'm just kinda reading the entrails
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<Jmabsd> sure. on my part I had a totally bizarre email exchange with IBM around 2017
<Jmabsd> about 60 mails to reach the conclusion that IBM cannot afford donating Power9 HW to OpenBSD to implement support, and I must be a bad person for proposing to IBM to do the obvious.
<Jmabsd> eventually someone else donated.
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<jrtc27> > their arch is proprietary so they are naturally out-competed by RISCV and ARM
<jrtc27> uh, that does not at all follow
<jrtc27> nor is the latter half even correct
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<Jmabsd> > uh, that does not at all follow
<Jmabsd> jrtc27: Intel has an excellent snowball of popularity, market traction, and some commercial advantage but not that big.
<Jmabsd> ARM and RISCV are, what is it called, incomplete ISA:s, there is a class of problems that POWER SPARC AMD64 solve and standardize where for ARM64 and RISCV, each computer will improvise solutions
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<Jmabsd> > nor is the latter half even correct
<Jmabsd> jrtc27: which part?
<jrtc27> RISC-V does not out-compete Intel
<jrtc27> RISC-V is still an immature ISA in places and the implementations are all woefully underpowered
<muurkha> interesting, which places?
<gordonDrogon> I never feel qualified enough to get into these sorts of discussions, but billions of dollars of investment and 30+ years is a lot to catch up on...
<gordonDrogon> however I'm slowly getting to grips with the esp32-c3 and realising it's not quite what I need... it seems to have some 'magic' hidden flash that it copies your uploaded program from into that precious RAM at boot time. Slightly disapointing but that 400KB of RAM is shrinking rapidly )-:
<muurkha> oh?
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<gordonDrogon> once you drill into the data sheets... 16KB is for cache and your code is copied into RAM.
<Jmabsd> > I never feel qualified enough to get into these sorts of discussions, but billions of dollars of investment and 30+ years is a lot to catch up on...
<Jmabsd> gordonDrogon: indeed RISCV has a lot to catch up with.
<Jmabsd> ARM64 is closer. And IBM Power is on par.
<Jmabsd> a Power10 and a Xeon are ballpark same same. ARM64 I guess... maybe slightly weaker per CPU core, but scale CPU cores quite well.. ARM N1 seems to become quite strong computationally?
<gordonDrogon> I've been well out of any sort of architecture level stuff for a very long time - it's all "commodity" for me now at that level. I'm using RV because it feels nice to me - in a very retro sort of way.
<Jmabsd> gordonDrogon: Sifive Unmatched is your primary computer? :-)
<gordonDrogon> I think it might be a long time before I have an RV desktop... but right now I can boot my retro BCPL OS onto an ESP32-C3 and it's like a zillion times faster than the old 65816 :)
<gordonDrogon> actually it's 10x the cpu clock 16Mhz vs 160Mhz) and about 60 times faster.
<gordonDrogon> hard to tell since I don't have a timer going yet.
* gordonDrogon wonders if I'm the first to run BCPL on RV ;-)
<gordonDrogon> suppe time here. back later.
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<Jmabsd> gordonDrogon: all you need is a Sifive Unmatched :)
<gordonDrogon> it's certianly an intersting board but sort of outside my requirements - the eternal problem - Ideally, I'm after a 32-bit cpu with 512KB RAM and peripherals ...
<gordonDrogon> but the majority are in the 32KB "microcontroller" range or GB 64-bit Linux range...
<gordonDrogon> this little M5 stamp board is a nice little proof of concept which I think I can make work - but also the Tang Nano 9K FPGA would be idea - if only I knew more (much more!) about FPGAs, VHDL and Verilog ...
<cousteau> "microcontroller" as in RV32E, or as in I but a small I?
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<gordonDrogon> more in terms of RAM, but RV32IM core
<gordonDrogon> it's a pure retro hobby project for me, nothing more, but the one thing I don't have more control over is the bcpl compile - it's evolved over the years and now needs a bit more RAM than it used to - I can make it compile most stuff in under 256KB though.
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<muurkha> gordonDrogon: I bet Richards would be thrilled to hear you have BCPL running on RISC-V
<cousteau> oh I see
<muurkha> under 256KiB but probably not under 64KiB
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<leah2> muurkha: we already have B running btw
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<muurkha> leah2: cool!
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<muurkha> you're compiling it though, not interpreting
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<muurkha> oh, I guess riscv64/ba.b compiles and riscv64/b interprets?
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<leah2> i think so, it's two staged
<leah2> see README
<cousteau> leah2: B as in the B extension?
<leah2> i didnt write the code, i just provided the machine :p
<leah2> B as the B language
<leah2> precedessor of C
<cousteau> oh
<cousteau> ...should've guessed it from the context
<cousteau> (BCPL is the predecessor of B, right?)
<leah2> yes
* cousteau points out that, technically speaking, the filename "ba.b" has a b extension
<muurkha> not the predecessor of the C extension, either
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<solrize> gordonDrogon, does it have to be riscv arch? there are other esp32 boards with psram, and there are some arm chips (teensy 4.0) with 1mb ram
<solrize> esp32-c3 has 400k ram is that not enough but 512k is enough?
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