sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<solrize> Including “And. And. And. And. And.” in a Google doc causes it to crash (support.google.com)
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<hanetzer> eyyyy. riscv not risc-v. so. I have a question about the sifive board. the spi/qspi device/peripheral it can boot from, can you hook up *any* kind of spi device to it, or is it purely for bootflash?
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<conchuod> Forgive my innocence hanetzer, but "the" sifive board? Which one specifically?
<hanetzer> tbqh I have no idea.
<hanetzer> so forgive my ignorance as I forgive your innocence :)
<hanetzer> I guess i'm more talking about the soc on it. yes, I know, nonspecific, but I'm unfamiliar with the riscv ecosystem. I'm just looking for a reference in the qemu tree to help model out another device's spi nand/nor flash controller
<conchuod> If you know which soc it is, it's probably worth looking up the schematic and having a look?
<hanetzer> well I mean. just because a given board doesn't have !flash hooked up to a given interface, doesn't mean it only supports flash.
<hanetzer> but yeah. I should figure out what real hw that qemu target is modeling.
<conchuod> For the hifive unleashed board, I think the qspi that's connected to the flash is not exposed otherwise but another qspi is
<hanetzer> 'RISC-V Board compatible with SiFive U SDK'
<conchuod> hmm, that unfortunately doesn't mean anything specific to me - I'd guess that means both HiFive Unleashed and Unmatched?
<hanetzer> SiFive HiFive Unleashed Development Board is the ultimate RISC-V development board featuring the Freedom U540 multi-core RISC-V processor.
<hanetzer> from the qemu readthedocs.io :)
<conchuod> QSPI1 should go to a header
<hanetzer> because, while this the chip I'm replicating has a 'standard' arm,pl022/arm,primecell spi controller, you can hook spi-*anything* up to that. the fmc controller, specific to hisilicon SoC's, is only good for spi-*flash(nand/nor)*
<hanetzer> specifically it more or less *must* boot from either of those
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<hanetzer> so you could have a nand bootflash and a nor !bootflash for general storage or the opposite.
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<conchuod> qspi0 on the unleashed is connectd to a issi is25wp256 and qspi1 is exposed to (multiple i think) headers
<hanetzer> so, could you hook a, for example, spi-based temperature sensor to the qspiN outputs?
<conchuod> I don't use my unleashed nor have I tried, but I don't see why not?
<hanetzer> gotcha, so its more a 'general purpose' spi bus
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