sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<lumberjack123> Does anyone know if RV64IMAFDCVU has libre HDL source available?
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<lumberjack123> This Maybe this is ISA not SOC model sorry
<sorear> correct, that's an ISA feature string, I don't think the HDL source is available for the D1 or its cores
<lumberjack123> sorear: How did you know I was talking about the D1
<sorear> because you just posted a link
<lumberjack123> I found this but "repo" is not working for me (I don't know why tey don't use plain git)
<lumberjack123> So I am not sure what is in the SDK yet
<lumberjack123> sorear: Oh yeah okay actually I am looking at ClockworkPi Core R-01
<sorear> repo is a google tool for managing multiple git repositories at once
<sorear> (in true google fashion, there are several of these)
<sorear> SDK = software development kit = generally means a compiler, linker, and sometimes OS components; a SDK will _not_ have HDL
<lumberjack123> It says XuanTie C906 RISC-V in this doc which IIRC is Apache 2.0 licensed online
<sorear> ah, that finally got published?
<lumberjack123> But this is from Allwinner not Alibaba so maybe they added more code and did not release it, it is not copylefted so they can do this legally.
<sorear> that's going to happen regardless
<lumberjack123> sorear: What do you mean regardless?
<sorear> any physical chip you're holding has a whole bunch of components from a whole bunch of companies, even if they use the core unmodified there are things there other than the core
<lumberjack123> What if it were copylefted?
<lumberjack123> Or would they just not be able to use the core becayse they can't get the other components from other companies under the same license?
<sorear> this is a linking situation so copyleft doesn't straigtforwardly apply
<sorear> not that there's enough legal precedent to know
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<la_mettrie> trying to understand how these systems work... VisionFive's pages tell you how to compile kernel but no word about making initramfs. actually update-initramfs and update-grub seem both to be absent on the Debian-build i have
<la_mettrie> at the same time i get errors like this which may suggest that initramfs should be updated: videobuf2_memops: version magic '5.4.61 preempt mod_unload riscv' should be '5.17.0-rc5-starfive-rc5 SMP preempt mod_unload riscv'
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<courmisch> do I understand right that LLVM implements 8- and 16-bit atomics by rounding down the address to 32-bit and then masking the other bits?
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<courmisch> so the actual storage size of the atomics is 8- or 16-bit, not 32-bit
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<cousteau> I'm curious about where did the N extension go. It seems that volume I of the standard moved the N extension to volume II, and volume II just dropped it... Did it get absorbed into another extension, was it temporarily abandoned, what happened?
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<cousteau> sorear: oh OK, so "remove it for now until we've decided what it'll actually look like"
<cousteau> I thought interrupts were on a more mature state
<dh`> the problem with N is that as it was written the OS _must_ handle it or it becomes a security problem
<dh`> or a problem
<cousteau> I see
<dh`> though I don't see why it needs anything more than an enable bit somewhere that usermode can't see
<dh`> (or maybe that it can see but not touch)
<cousteau> So it was more of a "hey, the way we initially approached this is extremely insecure, we will need to rewrite it from scratch" than a "this way to do things is much more convenient in practice"?
<jimwilson> lumberjack123, https://github.com/T-head-Semi But these are just cores not SoCs
<cousteau> dh`: maybe they haven't decided yet, and it might end up being just what you said, but until they've thought about it in depth they have preferred to just remove it
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<jimwilson> lumberjack123, and it isn't V, it is an draft version of V incompatible with the actual V standard
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<dh`> having a "V" for "RISC-V" always causes a momentary double-take
<sorear> cousteau: also N was redundant for its intended purpose. there was always the option to implement S mode and *not* implement paging (this is what bare S means in the commit message), which gives you exactly the same results as the N extension in a M/U system except for two more bits in mstatus
<dh`> I always figured the goal was more efficient interrupt delivery to microkernel drivers
<sorear> doesn't really help you for that purpose because if you're intentionally taking interrupts, it means you were doing something else, which means you have to go into the kernel to do a context switch
<sorear> it _would_ help for things like hardware assisted GC write barriers
<cousteau> sorear: interesting. I'm not familiar with the details, but I expected paging to be pretty much what a supervisor does..
<cousteau> ("paging" is virtual memory, right?)
<sorear> "pretty much" but the individual page table formats are all optional, and there's nothing actually in the spec to prevent you from implementing none of them
<sorear> (yes)
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<jrtc27> courmisch: yes, and gcc just calls into libatomic which does exactly the same thing internally; note it's an outstanding issue that gcc doesn't just do the same as llvm
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