<solrize>
i wondered if there was any defined extension for it and the answer is there is a proposal
<solrize>
i wonder if there is an fpga implementation
<solrize>
and how its speed would compare to software
raym has quit [Ping timeout: 252 seconds]
<solrize>
Due to the large opcode space required by the fused multiply-add instructions, the decimal floating-point instruction extension will require five 25-bit major opcodes in a 30-bit encoding space.
<solrize>
??
raym has joined #riscv
<solrize>
ah there is not really a draft, but tat least there is a placeholder for it
<sorear>
the binary FMA instructions use 1/3 of the 32-bit opcode space (or would, if all 8 rounding modes existed)
<sorear>
there is _not enough_ space in the 32-bit opcode map for a full set of decimal FMA instructions, so it'll have to either use 48-bit instructions or be restricted in some way (like 3-operand instructions, or dynamic rounding only)
<sorear>
there isn't much to actually innovate with decimal FP, IEEE 854 / 754-2008 covers the subject and it's in the C and C++ standards, but it's mostly an IBM thing right now
<solrize>
yeah it will be good if riscv supports it
<solrize>
there are 48 bit instructions? i didn't know that
<solrize>
sounds ciscy ;)
<sorear>
I wish people would stop using that term
<sorear>
it was coined to describe the VAX, which is _far_ worse than anything most people today are familiar with; to be blunt I would consider x86 a RISC architecture by the historical standards (typical instructions e.g. integer add can only access 1 memory location, compared to 4 on the 68020 and 6 on VAX)
<solrize>
well, variable length instructions with complicated decoding was another marker, though maybe less relevant now
<sorear>
riscv, arm, and s390x have a simple prefix code for instruction lengths
<sorear>
x86 is a complete mess mostly because of a lack of forward planning :/
<sorear>
low two bits NOT 11? 16-bit
<sorear>
low two bits 11, next 3 bits NOT 111? 32-bit
<sorear>
low 5 bits 11111, next bit 0? 48-bit
<sorear>
x86 and vax, well, you need most of the generality of regular expressions just to figure out where the instructions _are_
winterflaw has joined #riscv
epony has joined #riscv
pecastro has joined #riscv
<enthusi>
Hi, maybe someone here can help me. On the VisionFive/Fedore I get LLVM JIT errors when executing compiled binaries. NOw I dont even want LLVM do contribute to the building process at all. Those things worked ootb on the unmatched, so it's not strictly a riscv64 thingy. Any hints/ideas or experiences with that?
<enthusi>
'generic' is not a recognized processor for this target (ignoring processor) ...
<enthusi>
WARNING: This target JIT is not designed for the host you are running.
<enthusi>
but I dont even want JIT/LLVM, just plain GCC (dnf remove llvm already prior to compiling but to no avail)
<sorear>
"compiled binaries" is very vague, which binaries specifically are giving you those errors? strace -f -ewrite may help
<sorear>
(I haven't been following LLVM JIT at all but you shouldn't need it for compiling hello world with gcc)
<enthusi>
tested with scummvm (which always compiles cleanly) and c64 vice emulator
<enthusi>
I am recompiling after having removed clang as well and then will check with strace. JIT is likely the issue as it doesnt support rv64 yet, fully. It just shouldnt be used at all
winterflaw has quit [Remote host closed the connection]
<sorear>
especially if you can rule out scummvm directly using llvm (e.g. using lld)
<enthusi>
I just removed llvm libs that were still present and that mesa depended on
<enthusi>
so could be
<sorear>
presumably mesa is trying to use llvm jit on the visionfive because it doesn't have a GPU
<sorear>
whereas when you were testing on the unleashed it had a GPU so mesa didn't need to generate riscv code
<enthusi>
could very well be something like that
<enthusi>
(though I dont think scummvm even needs mesa, I compile directly for sdl2)
<sorear>
(honestly I've never tried, so I don't have much more specific advice than "take nothing for granted")
<enthusi>
libGL error: MESA-LOADER: failed to open swrast: /usr/lib64/dri/swrast_dri.so: cannot open shared object file: No such file or directory (search paths /usr/lib64/dri)
<enthusi>
libGL error: failed to load driver: swrast
<enthusi>
ok, so without mesa around it compiles but doesnt start, yet that is a more 'real' error here :)
<enthusi>
thanks I will continue under the assumption that mesa is the source
<enthusi>
(but not taking it for granted :)
BOKALDO has joined #riscv
<enthusi>
yeah, in this Fedora, mesa depends on llvm-libs etc ...
winterflaw has joined #riscv
<sorear>
(I should take my own advice and not say "presumably" - it is one possibility among many)
mauz has joined #riscv
jacklsw has quit [Ping timeout: 250 seconds]
mauz has quit [Quit: Leaving...]
lumberjack123 has quit [Ping timeout: 240 seconds]
lumberjack123 has joined #riscv
elastic_dog has quit [Ping timeout: 240 seconds]
tgamblin has quit [Ping timeout: 240 seconds]
tgamblin has joined #riscv
avoidr has quit [Ping timeout: 260 seconds]
avoidr has joined #riscv
<muurkha>
the SiFive FU740 manual explains its virtual memory support in §4.7 p.42: "The U74 has support for virtual memory through the use of a Memory Management Unit (MMU). The MMU supports the Bare and Sv39 modes as described in The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. SiFive's Sv39 implementation provides a 39-bit virtual address space using 38-bits of physical
<muurkha>
address space. ... The default Linux page size (PAGESIZE) is 4 KiB."
<muurkha>
so that answers my question. too bad the Unleashed and Unmatched and whatever are all gone now
<muurkha>
I haven't yet found the corresponding manual for the Allwinner D1 but I imagine it's about the same
elastic_dog has joined #riscv
raym has quit [Quit: rebooting...]
raym has joined #riscv
geranim0 has joined #riscv
EchelonX has joined #riscv
handsome_feng has quit [Quit: Connection closed for inactivity]
riff-IRC has joined #riscv
Sofia has quit [Ping timeout: 240 seconds]
Sofia has joined #riscv
Sofia has quit [Ping timeout: 240 seconds]
Sofia has joined #riscv
BOKALDO has quit [Quit: Leaving]
jacklsw has joined #riscv
BOKALDO has joined #riscv
aerkiaga has joined #riscv
mahmutov_ has joined #riscv
X-Scale` has joined #riscv
X-Scale has quit [Ping timeout: 256 seconds]
X-Scale` is now known as X-Scale
X-Scale` has joined #riscv
X-Scale has quit [Ping timeout: 272 seconds]
X-Scale` is now known as X-Scale
<jrtc27>
muurkha: Allwinner D1/T-HEAD C906 does not implement Sv39, it implements a non-standard variant that violates the spec
<jrtc27>
(but reuses the encoding for it)
<jrtc27>
enthusi: there is no generic, only generic-rv32 and generic-rv64