<Xark>
muurkha: UPduino 3.1 is a nice inexpensive DIP FPGA board for iCE40UP5K (with 128KByte of embedded SPRAM), I am using it in my retro video project. However, not ideal for typical RISC-V SoC, since single channel FTDI only lets you access SPI flash _or_ UART (not both in same design). Minor bummer if you want RISC-V with flash and UART (but can use external FTDI).
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<muurkha>
because Digi-Key doesn't carry UPDuino and I'm asking a friend to buy me the stuff and bring it to me
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<solrize>
muurkha, i thought you needed fancy pcb fab to make traces fine enough. also 6 layers is a lot. how many layers does a typical small dev board have?
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<Xark>
muurkha: Cool, that is a pretty nice board also (some good examples for it here https://github.com/damdoy/ice40_ultraplus_examples). However, I really don't like how they hooked FTDI to SPI. I find UART more useful (and SPI is a pain on PC side - but it is does have dual channel FTDI, for JTAG). I will also mention UPduino is now available more easily in EU from LectronZ https://lectronz.com/stores/tinyvision-ai-store
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<la_mettrie>
smaeul: this toolchain didn't find headers for compiling boot0: make CROSS_COMPILE=riscv64-unknown-elf- p=sun20iw1p1 mm
<la_mettrie>
so i had to use instead: make CROSS_COMPILE=riscv64-linux-gnu- p=sun20iw1p1 mmc
<la_mettrie>
dunno if this is just my stupid mistake, but i report anyway since README seems to suggest that ELF toolchain can be used (i downloaded it from my x86-debian's repository)