#osdev on 2024-11-05 — irc logs at libera.irclog.whitequark.org

2021-05-23 01:57 klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books

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07:59 <muffin> I have 16 local APIC structures in my MADT, 14 of which are marked as unusable. I only have 2 cores. Interesting design

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08:23 <Mutabah> Probably the firmware supports up to 16 cores, and only fills in the ones it needs

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08:29 <muffin> makes sense Mutabah

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08:32 <heat> what hardware is this?

08:32 <heat> that reeks of vmware, vmware has the nastiest acpi tables like this

08:33 <muffin> It's an Intel Celeron N4500

08:34 <muffin> with the acpi cpuid flag

08:34 <heat> heh okay

08:35 <heat> running on bare metal?

08:36 <muffin> No virtualization - I read out the ACPI tables directly through the UEFI configuration table RSDP

08:37 <heat> hmm what field are you referring to as "unusable"? i went to check my own code but there's no such field in the MADT...

08:38 <muffin> well, in the ACPI spec 6.5, 5.2.12.2 Processor Local APIC Structure it says "If this bit

08:38 <muffin> is clear and the Online Capable bit is also clear, this proces-

08:38 <muffin> sor is unusable"

08:39 <muffin> refering to the Enabled bit

08:41 <heat> ah okay, thanks

08:41 <heat> i should fix this

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12:22 <EmanueleDavalli> I managed to cross-compile binutils for my os, I'm happy

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12:51 <mid-kid> I want to run 32-bit code inside a 64-bit linux program, to be able to embed precompiled code inside of the program.

12:51 <mid-kid> Any tips on where I should look to do this? Does anyone have any examples?

12:54 <mid-kid> I don't need to be able to access 32-bit system calls, just jump from the 64-bit code to the 32-bit code, and call 64-bit functions from hooks I'll install in the 32-bit code.

12:58 <GeDaMo> I don't think you can call 32-bit code directly from 64-bit on x86, it might have to be a separate process

13:00 <sortie> mid-kid: Unless the Linux kernel has a syscall for switching a thread to 32-bit, that's not really possible. But see the x32 ABI which is a 32-bit subset of x86_64.

13:00 <sortie> mid-kid: Can you tell us more about your motivation? Why don't you just embed 64-bit code?

13:00 <mid-kid> I don't suppose x86_64 instructions are encoded the same as x86 instructions?

13:01 <sortie> They kinda are but not 1:1 and they don't quite mean the same thing

13:01 <mid-kid> yeah that doesn't work for me

13:01 <sortie> Very similar but different

13:01 <GeDaMo> Some 32-bit instructions have been repurposed

13:01 <sortie> You got some binary blobs you want ro run?

13:01 <mid-kid> I got binary blobs yeah

13:02 <sortie> If they don't need system calls, I'd say spawn a 32-bit child process to run the binary blobs and use IPC to do RPCs into them

13:02 <sortie> Can you tell us more about the nature of these binary blobs?

13:02 <mid-kid> This is the project: https://github.com/mid-kid/metroskrew/ I extract code from a windows exe, patch it, and execute it.

13:02 <bslsk05> mid-kid/metroskrew - Port of the proprietary Windows Metrowerks ARM compiler to Linux by relinking (0 forks/4 stargazers)

13:03 <mid-kid> Right now it runs as a 32-bit binary

13:03 <sortie> Aha. And Wine isn't good enough for you?

13:03 <mid-kid> But I was wondering if I could make it a 64-bit binary without too much fuss

13:03 <sortie> Because that is kinda what wine is

13:03 <mid-kid> WINE is slow as molasses

13:03 <mid-kid> especially for things like this (a compiler) that is expected to be called thousands of times in short succession

13:04 <sortie> Making it a 64-bit binary is basically making it a 32-bit binary and just running it under a 64-bit kernel

13:04 <sortie> Unless you replace large parts of it with your own code and only got a couple tiny blobs

13:05 <mid-kid> hmm

13:06 <mid-kid> I did hear from somewhere that it's possible to jump to 32-bit code by reconfiguring some things, as long as you don't need syscalls.

13:06 <mid-kid> But I fail to remember what they mentioned about it.

13:07 <sortie> From a kernel point of view, totally doable, you can do that with the GDT and special instructions. Basically some of the first things you learn in osdev. You have to be the kernel though.

13:07 <sortie> So for your purposes, the question is whether Linux has a system call that can do this. For all I know, it might. wine could be using it.

13:08 <mid-kid> Yeah that's the thing that spurred this on

13:08 <sortie> mid-kid: But are the blobs 99% of your process? Or have you written a lot of code around them?

13:08 <mid-kid> WINE is implementing a method of running 32-bit programs without needing 32-bit libraries and support

13:08 <mid-kid> And I'm not sure what it's doing to accomplish that

13:08 <mid-kid> Surely it has wrappers to cross the boundaries at a win32 API level but

13:08 <sortie> wine acts as the dynamic linker

13:09 <mid-kid> sortie: the wrappers are most of my process

13:09 <mid-kid> sorry the blobs are most of my process

13:09 <sortie> In that case, you don't get any benefits from 64-bit.

13:09 <mid-kid> what I'm seeking is supporting userspaces without 32-bit support like WSL1

13:10 <mid-kid> the processor supports 32-bit no matter what

13:10 <mid-kid> just userspaces are all over the place

13:10 <sortie> If you want to run a Linux 32-bit program on on any platform, qemu-i386 is handy: https://www.qemu.org/docs/master/user/main.html

13:10 <bslsk05> www.qemu.org: QEMU User space emulator — QEMU documentation

13:10 <sortie> It basically translates the program dynamically to your native instruction set

13:11 <mid-kid> not really an option when I'm seeking speed lol

13:11 <sortie> qemu is fast especially with kvm

13:11 <sortie> The qemu-user mode doesn't emulate an entire OS, it just translates one process

13:11 <mid-kid> the alternative to this would be dumping all the ASM and writing a static recompiler for a few key CPUs

13:11 <sortie> mid-kid: But if you want fast? You got a 32-bit Linux process. Just run it.

13:12 <sortie> It works on 64-bit Linux too. Try static linking if you can't rely on a runtime.

13:12 <mid-kid> not an option on WSL1

13:12 <mid-kid> niche platform but eh

13:12 <sortie> Well if you can't afford a Linux system then I don't know what to say :)

13:12 <mid-kid> lol

13:13 <mid-kid> it was also just curiosity

13:13 <mid-kid> since I know it's possible

13:13 <mid-kid> maybe I should ask the WINE devs

13:13 <sortie> In any case, this is kinda a bit outside the realm of osdev, although I do see how this is a project that kinda falls through the cracks of established communities

13:13 <sortie> Wine devs might definitely know more about cursed Windows and Linux stuff

13:14 <mid-kid> true, I'm just not aware of many low-level tinkering communities on the internet

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13:15 <sortie> Totally. This is a fine place to ask. Just that, you know, most people here mostly spend time on their own osdev projects and might not know cursed corners of the Linux kernel :)

13:15 <mid-kid> seeking help with this project, involving a bunch of quirks of ELFs, binutils and linux/windows APIs, has been naught impossible in general :)

13:15 <mid-kid> thankfully I didn't end up needing a lot of it but if there's anyone that knows about CPU states and segments it's you guys

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13:15 <sortie> I'm afraid it's going to be a lot of getting fragmented information from here and there

13:16 <mid-kid> hehehe

13:16 <mid-kid> I'm like 90% there, porting this to other platforms may be a goal in the future but nowhere in the near future

13:17 <mid-kid> I just wondered if I could get away with a filthy 64-bit port for now

13:17 <mid-kid> anyways, thanks for entertaining my questions :)

13:17 <GeDaMo> Could you use something like qemu to do a one-off translation?

13:18 <mid-kid> I'm not sure what you mean?

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13:19 <GeDaMo> Translate from your 32-bit code to 64-bit code

13:20 <GeDaMo> Normally, qemu translates at run-time, I'm just wondering if it can do an ahead-of-time translation

13:20 <mid-kid> I don't think it can, but it's something I've been musing doing myself

13:21 <mid-kid> it's not a very rogue binary that pulls nasty tricks so I could make a bunch of assumptions

13:21 <mid-kid> problem is mostly I can't get away with just dumping and manually inspecting the asm once

13:21 <mid-kid> there's like 24 versions of this compiler I want to support

13:21 <mid-kid> and its assembler, and its linker

13:22 <mid-kid> currently I have a program that analyzes the PE data and looks for certain function signatures

13:22 <mid-kid> to automatically fix things up and patch some functions

13:24 <mid-kid> AOT translation would require correctly identifying all functions, references to rodata, and etc

13:25 <mid-kid> programs like radare2 and rizin do a decent but not perfect job at that, so I kind of doubt QEMU is equipped to tackle that problem.

13:26 <mid-kid> anyway, thanks again, and sorry for flooding the channel

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13:49 <heat> mid-kid, you most definitely can run 32-bit code in a 64-bit program

13:49 <heat> i'm 99% sure you can just switch segment registers and it Just Users

13:49 <heat> Just Works

13:49 <heat> not just users obviously

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13:53 <heat> basically keep a thunk in a 32-bit region, switch data segment registers (ds, ss, fs, gs, es) to a 32-bit segment, then long jump with a 32-bit compat segment

13:53 <heat> this is very likely to be what wine does

13:53 <mid-kid> aha!

13:54 <mid-kid> that tracks more closely to what I heard

13:55 <mid-kid> are there any examples of this on the osdev wiki? is this 32-bit compat segment documented anywhere in linux?

13:55 <mid-kid> (idk is a valid answer lol)

13:58 <heat> https://elixir.bootlin.com/linux/v6.11.6/source/arch/x86/include/asm/segment.h#L212

13:58 <bslsk05> elixir.bootlin.com: segment.h - arch/x86/include/asm/segment.h - Linux source code v6.11.6 - Bootlin

13:59 <heat> let me draft up some asm for you

14:00 <mid-kid> ooooh, that'd be super helpful

14:02 <mid-kid> ah, so the __USER32_CS is the segment I want to jump to

14:02 <mid-kid> I assume I'll need to make sure that the program is located in 32-bit addressable memory

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14:03 <mid-kid> -fno-pie goes a great way towards that goal

14:03 <heat> https://gist.github.com/heatd/1ab09ceaa2a743da17799bebf77c94e9

14:03 <bslsk05> gist.github.com: switch32.S · GitHub

14:04 <mid-kid> oh, you can abuse lret instead of jmp cs:addr

14:04 <sortie> heat: That actually works in user-space?

14:04 <heat> 99% sure yeah

14:04 <heat> you just can't switch privilege rings

14:05 <GeDaMo> The best way to get an answer is to say something wrong on the Internet :P

14:05 <heat> basically you need that thunk in 32-bit space, plus your 32-bit code and data in 32-bit space (mmap MAP_32BIT in linux gets you there)

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14:06 <mid-kid> Neat, I'll draft up a way to build a binary that does this

14:06 <mid-kid> I want to see if this works in WSL1, in particular. I think that'd be neat.

14:06 <mid-kid> Thanks a lot!

14:07 <heat> you're welcome :)

14:08 <heat> hmm actually those two lret's may be problematic

14:08 <heat> switch them out to a ljmp if you can

14:09 <heat> because 1) PIE 2) pushl might overflow your relocations 3) textrels

14:09 <mid-kid> alright!

14:14 <zid`> mmm textrel

14:14 <zid`> tastey flightless bird

14:21 <Ermine> https://www.shielder.com/blog/2024/01/hunting-for-~~un~~authenticated-n-days-in-asus-routers/

14:21 <bslsk05> www.shielder.com: Shielder - Hunting for <del>Un</del>authenticated n-days in Asus Routers

14:22 * Ermine has asus router and kinda scared

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14:22 <Ermine> is kinda scared*

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14:35 <zid`> I honestly think the various libcs should harden around %n

14:35 <zid`> disable it by default somehow

14:35 <heat> they do

14:35 <zid`> oh?

14:35 <zid`> works fine for me with glibc

14:36 <heat> they do _harden_

14:36 <heat> they don't disable it by default

14:36 <zid`> right

14:36 <heat> actually macOS might? idk

14:36 <heat> or openbsd for the weirdos

14:36 <zid`> %n is almost always just used in attacks and not in actual software, tbh

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14:43 <heat> the beauty of glibc is that i can't find printf

14:44 <zid`> too enterprise for heat

14:44 <heat> i'm a fan of REAL CODE for REAL PROGRAMMERS

14:44 <heat> not this soyboy definefest

14:45 <zid`> I mean, I am too, but, there's often a sadge reason

14:45 <zid`> like having to support weird things like onyx

14:45 <zid`> or strange compilers like llvm

14:45 <zid`> or *shudder*, wide characters

14:50 <heat> nah this is just gnuware

14:51 <zid`> glibc is slightly too over-enginereed but probably not by that much once you get into it

14:53 <Ermine> everything becomes simpler once you get the idea

14:53 <heat> i wasn't understanding why a variable existed in a function, but wasn't assigned to, ever (readonly_format)

14:53 <heat> turns out they do this in a .c that is then #include'd into a function, twice!

14:54 <Ermine> gnu folks like doing this

14:54 <nikolar> what do you mean heat

14:54 <netbsduser> i like a lot of gnu things but they have elevated pissing on C to a high art

14:55 <heat> https://elixir.bootlin.com/glibc/glibc-2.40.9000/source/stdio-common/vfprintf-process-arg.c#L325 half of these identifiers aren't actually identifiers but macros

14:55 <Ermine> there's another lib by gnu, which does the same thing

14:55 <bslsk05> elixir.bootlin.com: vfprintf-process-arg.c - stdio-common/vfprintf-process-arg.c - Glibc source code glibc-2.40.9000 - Bootlin

14:55 <netbsduser> it's rotten

14:55 <netbsduser> i did some awful stuff in a similar vein when i was very new to c

14:56 <heat> nikolar, https://elixir.bootlin.com/glibc/glibc-2.40.9000/source/stdio-common/vfprintf-internal.c#L125 readonly_format

14:56 <bslsk05> elixir.bootlin.com: vfprintf-internal.c - stdio-common/vfprintf-internal.c - Glibc source code glibc-2.40.9000 - Bootlin

14:56 <nikolar> > # define OTHER_CHAR_T wchar_t

14:56 <nikolar> kek

14:57 <netbsduser> then i realised slowly by exposure to real C code that you don't just go writing "c", you should study the bsd, solaris, or even the linux codebase to learn how you write real C

14:57 <Ermine> that's where musl wins actually

14:57 <zid`> I hate reading code so I didn't bother to study

14:57 <zid`> I just saw lots of garbage and avoided it :P

14:57 <Ermine> even with dns_parse and friends

14:57 <zid`> people asking for help and stuff

14:57 <nikolar> zid` loves write only code

14:57 <zid`> correct

14:57 <zid`> code is for *compilers* to read, not people

14:57 <zid`> If you don't like the code, delete it

14:57 <zid`> and write it again

14:58 <heat> in rust

14:58 <zid`> in rust you delete it and rewrite it all anyway, because you changed one variable's lifetime

14:59 <nikolar> kek

14:59 <netbsduser> long story short, if it isn't in kernel normal form or a cognate thereof also derived from kernighan and ritchie's own style, if the codebase doesn't know how to do generic intrusive lists with macros, it's not really C and you ought to avoid it

14:59 <zid`> fuck generic lists

14:59 <zid`> too enterprise

14:59 <nikolar> at least intrusive lists are almost trivial to do

14:59 <nikolar> even inc

14:59 <nikolar> *in c

14:59 <zid`> just throw a fucking struct n *next; in by hand ffs

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15:01 <zid`> send_msg or whatever it is in the linux api can also fuck off

15:01 <nikolar> lol

15:02 <zid`> "let's implement a very simple packet format using only 'clever' macros"

15:03 <nikolar> kek

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20:01 <mid-kid> heat: https://gist.github.com/mid-kid/52114a0360e8c90cd626bbeebe93a102

20:01 <bslsk05> gist.github.com: bits.s · GitHub

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20:01 <mid-kid> This is what I got so far

20:02 <zid`> I've never seen anybody ship source as a batch file that compiles itself

20:02 <zid`> it makes sense, but I've just never seen it

20:03 <mid-kid> I want to eventually wrap this in C to make it easier to work with but

20:03 <mid-kid> I'm wondering why the `ljmp [1f]` code is segfaulting on me

20:03 <heat> define not working?

20:04 <zid`> because you're running 'long offset 1f' as code?

20:04 <mid-kid> heat: It segfaults at that `ljmp [1f]` instruction if you uncomment the section and comment the inmediate ljmp

20:04 <zid`> oh wait is that

20:04 <zid`> ljmp

20:04 <heat> what does dmesg say?

20:05 <mid-kid> it's assembled as `ff 2d xx xx xx xx` where xx is an absolute address (which is fine due to -no-pie)

20:05 <heat> ah you're testing this in WSL1? might not give you a decent dmesg

20:05 <mid-kid> https://github.com/wine-mirror/wine/blob/master/dlls/wow64cpu/cpu.c#L321

20:05 <heat> let me test locally

20:05 <bslsk05> github.com: wine/dlls/wow64cpu/cpu.c at master · wine-mirror/wine · GitHub

20:05 <mid-kid> WINE does the exact same thing

20:05 <mid-kid> so I wonder what I'm doing wrong

20:05 <mid-kid> <heat> ah you're testing this in WSL1? might not give you a decent dmesg <- nah I'm running native linux

20:05 <mid-kid> I'll test WSL1 later

20:05 <mid-kid> one sec I'll grab a dmesg

20:06 <heat> runs here?

20:06 <zid`> I keep forgetting ljmp exists and isn't just people talking about jmping in gas

20:06 <mid-kid> heat: did you comment the `jmp __USER_CS:2f` line?

20:07 <mid-kid> [208024.702287] traps: bits.s.elf[971] general protection fault ip:401150 sp:ddd063e8 error:0 in bits.s.elf[401000+1000]

20:07 <mid-kid> waaaait

20:07 <mid-kid> is this a CET thing

20:07 <heat> unlikely

20:08 <zid`> # ./midkid.s.elf

20:08 <zid`> main: 0x0000000000401126

20:08 <zid`> aaa: 261

20:08 <heat> i mean if it works without the [] i'm happy

20:08 <mid-kid> let me upload the exact segfaulting version

20:08 <heat> i don't immediately see why the indirect jump wouldn't work

20:08 <zid`> do I need to uncomment anything

20:08 <heat> wait, reload segment registers?

20:08 <heat> i did tell you to do that

20:09 <mid-kid> https://gist.github.com/mid-kid/52114a0360e8c90cd626bbeebe93a102

20:09 <mid-kid> heat: Is that it, really?

20:09 <heat> maybe?

20:09 <zid`> # ./midkid.s

20:09 <zid`> main: 0x0000000000401126

20:09 <mid-kid> yeah it segfaulted now

20:10 <mid-kid> Oh I guess [1f] is a data reference, so a data segment being wrong would mess it up

20:10 <zid`> [1328864.050223] RIP: 0023:0x401154

20:10 <zid`> [1328864.050578] Code: 00 00 00 48 8d 35 f2 ff ff ff 31 c0 e8 f5 fe ff ff b8 0f 00 00 00 48 89 25 ca 2e 00 00 ff 2d 00 00 00 00 53 11 40 00 23 00 37 <ff> 2d 5a 11 40 00 60 11 40 00 33 00 48 8b 25 aa 2e 00 00 48 8d 3d

20:10 <mid-kid> hmm

20:10 <zid`> crashed on the ff 2d 5a 11 40 00

20:10 <mid-kid> yeah

20:10 <zid`> 401154: ff 2d 5a 11 40 00 jmp FWORD PTR [rip+0x40115a]

20:10 <heat> hmm, for one, might not be needed, data segments don't have bitness

20:10 <mid-kid> I've just been unable to find the __USER32_DS value

20:11 <mid-kid> so I figured they stayed the same

20:11 <heat> otoh i anecdotally needed to switch for my kernel code, apparently

20:11 <zid`> 0x401160 0x33

20:11 <zid`> where do these user32cs and usercs come from? hardcoded in linux's gdt?

20:11 <heat> yes

20:11 <mid-kid> yeah

20:12 <mid-kid> yep, loading the segment registers fixed it

20:13 <mid-kid> damn, ok

20:13 <heat> okay there you go :)

20:13 <mid-kid> updated gist

20:13 <mid-kid> thanks a lot!

20:13 <zid`> why does it crash though

20:13 <heat> you're welcome :)

20:13 <heat> yeah i wouldn't know honestly

20:13 <mid-kid> zid`: [1f] imples ds:[1f] I think?

20:14 <zid`> right but your ds should be valid to begin with

20:14 <mid-kid> let me gdb it

20:14 <heat> gdb won't tell you much

20:14 <heat> actually gdb will probably royally blow up

20:14 <zid`> you need the error code from the gpf

20:14 <mid-kid> nah gdb has no issue with it

20:14 <zid`> if it's set to a number, it means you loaded an invalid descriptor, otherwise you go down a fuckin huge list of reasons :P

20:14 <mid-kid> ds is 0 after the ljmp

20:14 <heat> error is 0

20:15 <heat> oh? okay then, that makes sense

20:15 <mid-kid> ss is set correctly

20:15 <zid`> oh, is linux doing the '0 selectors are weirdly valid' thing

20:15 <mid-kid> and es is cleared

20:15 <heat> no

20:15 <zid`> which then blows up on the *next* transition

20:15 <heat> i mean, maybe

20:15 <heat> idk

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20:15 <zid`> you can leave a bunch of selectors 0 when you iretq back to userspace

20:15 <heat> segment registers and their context switching is hard and annoying

20:15 <mid-kid> I think ds and es aren't used in 64-bit mode at all

20:15 <mid-kid> so linux doesn't set them

20:15 <mid-kid> they're not set in main: either

20:16 <zid`> and they don't explode unless you try to fuck with them.. like we're doing here

20:16 <zid`> ss can also be 0 I think, weirdly?

20:16 <mid-kid> yeah, setting ds as the first thing in main() works too

20:16 <zid`> nod, solved imo

20:16 <mid-kid> it's preserved across the switch

20:16 <mid-kid> thanks again

20:16 <heat> this is for all the haters that said it couldn't be done

20:16 <heat> it can be done, it is discussing, and you just did it

20:17 <heat> disgusting

20:17 <zid`> I never would have thought of it, but I guess it's just.. fine? lol

20:17 <zid`> how do the syscalls react?

20:17 <zid`> don't give a shit because they reload cs anyway?

20:17 <mid-kid> I wouldn't dare execute syscalls like this

20:17 <heat> gotta make legacy syscalls with their numbers i believe

20:17 <heat> but yeah obviously reloads cs

20:17 <heat> this is getting into a 32-bit compat mode process, manually

20:17 <zid`> you'd wanna use the old ones just to get low pointers

20:18 <zid`> but I mean, theoretically, if everything was mapped low enough.. could you use the proper ones? :D

20:20 <heat> hmm actually it seems that 32-bit syscall emulation is one thing you can't poke from userspace

20:20 <zid`> even through int 0x80?

20:21 <zid`> I have no idea how linux even knows whether you're a 32bit or 64bit process unless that's how, int 0x80 vs syscall

20:21 <heat> oh wait, you might just be able to, through int 0x80

20:21 <heat> or even 32-bit sysenter/syscall, which it seems you can differentiate

20:21 <zid`> oh can you size modrm it

20:21 <zid`> then it dispatches differently in the cpu

20:21 <zid`> and linux can TELL

20:22 <heat> wdym

20:22 <zid`> syscall vs .byte 0x67 syscall

20:23 <zid`> which then does something.. different? I've never done a 32bit syscall syscall

20:23 <heat> that's a funky idea but i don't think that's what they do

20:23 <zid`> my worry is just that half the backend isn't set up

20:23 <zid`> like, a 32bit process not having a bunch of MSRs filled out for 64bit syscall to work, but in reverse

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20:29 <kof673> re: batch files with source, when i was talking about pragma stuff a long time ago, doug16k said ms stuff used pragma, not sure if that was just command-line flags or what. not the same but...

20:29 <geist> i'd think linux would just store somewhere that its a 32 or 64

20:30 <geist> like in the current thread structure

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20:32 <heat> yeah but apparently not

20:33 <heat> okay it seems they always assume int 0x80 is 32-bit

20:34 <heat> you could totally do it by segment register though (if cs == USER32_CS, compat syscall)

20:34 <zid`> sounds slow

20:34 <zid`> for no benny feet

20:34 <zid`> does 32bit syscall exist

20:35 <zid`> ah no

20:35 <zid`> Compat/Leg Mode, Invalid

20:35 <zid`> sysenter is both though

20:36 <zid`> IA32_SYSENTER_EIP (MSR address 176H) — The value of this MSR is loaded into RIP (thus, this value references the first instruction of the selected operating procedure or routine). In protected mode, only bits 31:0 are loaded.

20:36 <gog> on AMD yes

20:37 <zid`> let's do 32bit sysenter and 64bit syscall

20:37 <zid`> and int 0x80 calls rand()

20:37 <heat> it works nicely in practice because no one ever did/was able to do sysenter/syscall directly

20:37 <heat> always through the vDSO, and in that case they can just make it int 0x80

20:38 <heat> in case they don't use the vdso, always int 0x80

20:38 <geist> i guess the question there is can you int 0x80 from 64bit. ie, does the IDT get changed when you switch modes?

20:39 <geist> if they do switch or otherwise disable it in 64bit mode then coming through int 0x80 is prooof enough that it came from 32bit

20:40 <heat> you can't

20:40 <heat> 0x80 is always compat

20:40 <geist> i forget the detail there how that's disabled (or is it just implicitly disabled in 64bit mode?)

20:40 <geist> been a whiel since i thought about those details

20:43 <geist> now i'll have to re-read sysenter vs syscall. alls i remember is sycall is the only one used in 64bit on most systems, and usually sysenter is used in 32bit. some of it is because of availability on different cpus due to intel vs amd and for the longest time neither implementing both fully

20:43 <geist> syscall is always implemented in 64bit because it was part of amd64 from the get go so intel was forced to implement it

20:43 <geist> and thus it is the defacto 64bit mechanism

20:43 <heat> yea

20:44 <geist> even if syscall wasn't 'their' design

20:44 <heat> iirc intel implements sysenter in 32-bit and 64-bit, syscall only in 64

20:45 <geist> yah, and eventually amd implemented both in 32bit but since only sysenter is really available there on all cpus, no one bothers implementing syscall in 32bit

20:45 <geist> since IIRC they're about the same speed

20:46 <geist> iirc sysenter was added in P3. i remember running benchmarks on it on my P3 back in the early 2000s and it was indeed much faster

20:46 <geist> or more to the point the int mechanism on that class of machine was hundreds of cycles

20:46 <geist> and syscall/sysenter does like 1/10th of the work

20:53 <heat> now we just need to benchmark FRED

20:55 <zid`> Can we benchmark FRED on a pentium 3 though

20:55 <zid`> they'll bundle it with some awful modern intel cpu sadl

20:55 <zid`> with 28 cores clocked at 1GHz

20:55 <zid`> and 4 pci-e lanes

20:56 <heat> 2 P cores and 48 E cores

20:56 <heat> when you touch avx512 is halves the frequency

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20:58 <zid`> laptop only

20:58 <zid`> 20W part

20:58 <zid`> for some reason doesn't have xsave or avx2, but has 512

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21:06 <nikolar> Just wait for amd to do it properly

21:13 goliath has quit [Quit: SIGSEGV]

21:19 <zid`> what a world we live in

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21:55 <nikolar> Indeed

21:55 <nikolar> Btw geist, apparently -mapxf was enough to get 3 address instructions

21:55 <nikolar> GCC 14.2

21:56 <geist> nikolar: oh yeah i forgot to follow up. fiddled around with godbolt and got it to generate some apx stuff

21:56 <nikolar> Yeah same heh

21:56 <geist> i never could get it to really use the upper registers, but i'm sure if i gave it a complicated enough algorithm it eventually would spill over

21:56 <geist> in general i was seeing it use apx to use 3 address stuff to replace a alu + mov instruction sequence

21:56 <geist> and not much morer than that

21:56 <geist> in both clang and gcc

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22:03 <karenw> So the x86 lapic LINT0/1 registers have a 'type' and a 'vector'. What happens if I put 'type=NMI' and 'vector!=0x2'?

22:05 <nikolar> Yeah, I imagine 16 registers is quite enough for a vast majority of code

22:05 <nikolar> At least simple stuff you're messing with

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22:14 <zid`> karenw: presumably, your nmis stop working, if that's what it's supposed to be

22:15 <karenw> zid`: Fair, but would it route NMIs to a different vector, or would they come in on vector 0x2 regardless, or would hilarity ensure?

22:16 <zid`> I think those vectors are actually prios?

22:17 <karenw> Ah, that makes sense, it would just use the priority class of the vector.

22:17 <karenw> And ignore the least significant nibble

22:17 <zid`> I'm not sure you actually *have* anything connected to lint1 though

22:18 <zid`> lint0 is the pic and lint1 is the nmi line, I think, on a PC mobo

22:18 <zid`> and the nmi line is like, hardware watchdog

22:18 <karenw> Yeah, that's what I understand from the intel MP spec.

22:18 <zid`> if your server mobo has one

22:18 <karenw> There could be x86 devices out there with different configs, but they wouldn't be a 'PC-compatible' at that point.

22:19 <gog> NEC PC-98 for example

22:19 <heat> why are you reading the intel mp spec?

22:20 <zid`> MPS is what covers the APIC

22:20 <zid`> The SDM just says "read the MPS"

22:20 <zid`> no idea if it's *useful* to do that, but it does say it :p

22:20 <zid`> acpi is a superset of mps I think?

22:22 <karenw> The MP spec covers how the I/O apic, lapic, legacy pics are all wired together.

22:22 <karenw> That's the only chapter I'm reading anyway

22:22 <zid`> once you've read all this, tell me how msi works kthx

22:23 <karenw> zid`: Not in the MP spec, it only goes up to PCI bus not PCIe

22:23 <zid`> Once you've read all of the things, tell me how msi works kthx

22:23 <karenw> Willdo lol.

22:23 <karenw> Interrupt handling is a giant rabbit hole. I should have just gone with "Turn the legacy pics back on and pretend I'm Windows 3.1"

22:24 <zid`> My PCI-E interrupts arrive over the INT# thing and magically work and that's all I care about, the rest is fucking voodoo that I will not be touching unless it's to upgrade it to MSI from some well written notes :P

22:25 <karenw> I still haven't even got lapic/ioapic working. I just want to see keyboard interrupts (hoping that doesn't mean setting up USB)

22:25 <zid`> legacy usb in bios enabled makes it show up as ps/2 data I think

22:25 <zid`> via fakery involving SMI/SMM, was my assumption, but I never checked

22:26 <gog> that's about right

22:26 <gog> iirc

22:26 <zid`> cpu catches usb interrupt inside smm handler, it re-posts it as fake ps/2 data and returns, was my guess

22:26 <zid`> until you disable usb legacy on the controller and deliver it to 'yourself' instead

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22:32 <kof673> > NEC PC-98 yes, and there is djgpp for whatever dos that is, good gog

22:33 <gog> GOGDOS

22:34 <zid`> I'll stick to GLADOS

22:34 <zid`> At least she'll berate me while I die

22:34 <gog> and cake

22:34 <zid`> every man's dream

22:34 <zid`> cake and being berated by a woman

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22:43 <karenw> Christ, more random config I haven't found documented anywhere. Should lapic interrupts be level or edge? Limine leaves LINT0/1 as level and the rest as edge.

22:43 <heat> interrupts should be whatever the ACPI tables tell you

22:43 <zid`> PCI is level

22:43 <karenw> I'll leave them as level then

22:44 <karenw> Until I bother to parse ACPI

22:44 <zid`> It just depends what's connected to it, I'd just assume that whoever wired it up in your firmware left it wired correctly, shrug

22:44 <zid`> it'll be good enough for the keyboard and network to work I'd assume

22:44 <zid`> because of uefi supporting both internally

22:46 <heat> you need to parse ACPI

22:46 <zid`> If it doesn't work, buy a new computer where it does work*

22:46 <heat> IRQs with the wrong polarity will fuck your shit up

22:47 <karenw> Does ACPI also tell me what vector I should use for each LVT register? Or is that something my OS picks?

22:47 <karenw> And if it's configured to ExtINT, the vector I pick just acts as the base vector? Urgh, confused myself again

22:48 <heat> i don't remember what none of that shit is

22:48 <zid`> lint0/lint1 are the two legacy 'interrupt' pins, everything else is the fancy modern ioapic stuff

22:48 <heat> as far as i know you can skip everything

22:48 <heat> except the real pins

22:49 <heat> and the spurious irq thing

22:49 <zid`> so either you ignore the apic and just use lint0 via the pic, or you go all in on the apic and tell everything to deliver to the ioapic

22:49 <zid`> and disable the pic

22:49 <zid`> hope that helps

22:49 <karenw> The lapic timer also is useful and architectural.

22:49 <karenw> Or ignore the lapic and use the PICs directly

22:49 <zid`> you then program the ioapic to send an interrupt to a certain core's lapic

22:50 <heat> oh LVT is the timer

22:50 <heat> okay yeah you can pick whatever you'd like

22:50 <karenw> But you can't do SMP without the I/O apic mode

22:50 <zid`> You only need to bump the wakeup interrupt though

22:50 <zid`> not actually *use* them

22:50 <heat> vectors are purely a CPU thing, ACPI won't tell you anything, you can lay vectors out as you'd like

22:50 <karenw> LVTT is the timer LVT.

22:50 <zid`> lapic configuration is the final step, for 'what do with interrupt?'

22:51 <zid`> vectoring, masking, etc

22:51 <zid`> acpi tables are mostly full of "this is what's sending what to the ioapic" and "this is what's connected to lint0 and lint1" and stuff, lapic is internal and cpu controlled, the rest is how wires are connected

22:51 <heat> btw ISA interrupts (pin <= 19 it seems) need to be active-high, edge triggered, fixed delivery

22:52 <zid`> and needs the tables

22:52 <heat> was just checking my code

22:52 <zid`> everything should be active high edge

22:52 <zid`> people who do level and low are monsters

22:52 <karenw> https://pastebin.com/5bnnmDGE That's my current config. I guess it's time to actually parse ACPI to learn how to configure the I/O APIC. Maybe it will also reveal some lapic stuff I haven't learned yet.

22:52 <bslsk05> pastebin.com: (qemu) info lapicdumping local APIC state for CPU 0 LVT0 0x00008730 activ - Pastebin.com

22:55 <karenw> I still don't know what half of those registers actually are.

22:57 <heat> would love to help but uhhhhhhhhh i last looked at a lot of those bits either 3 or 7 years ago

22:58 <zid`> I'd have to check qemu source

22:59 <zid`> cus lvtpc isn't anything

22:59 <karenw> I still don't understand what 'ExtINT' mode actually doex

23:00 <zid`> I think it's talking about legacy pic

23:00 <zid`> when it says that, but it's a guess, qemuism again I think

23:00 <karenw> zid`: I assume it's the "LVT Performance Monitoring register", but QEMU is using an acronym for "Performance *Counter*"

23:01 <zid`> ooh clever

23:02 <karenw> Since LVTERR/LVTTHMR map to the LVT Error and LVT Thermal Sensor so that's the only one that's left.

23:02 <karenw> Although intel says all three of those are non-archetectural so I'm ignoring them for now

23:04 <zid`> for keyboard all you need to do is set the ioapic to deliver ps/2 interrupts via the apic not the pic, and disable the pic

23:04 <zid`> and to deliver it to a core that you actually have onlined, ofc

23:05 <karenw> I should have the PIC disabled correctly.

23:05 <zid`> doesn't your paste say you have it mapped to interrupt 48

23:05 <zid`> I mean, that's probably also fine

23:05 <karenw> LINT0 is mapped to interrupt 48. But the PIC itself is offline.

23:05 <zid`> like, if it never sends anything, that's also disabled

23:05 <zid`> yea

23:06 <karenw> There's a config register somewhere to re-route interrupts directly to the I/O apic I need to check that's set (it probabally is) and then actually unmask the IO APIC

23:06 <zid`> and the acpi tells you what's connected to each 'external' pin on the ioapic, and the ioapic can then route it to a specific pic

23:06 <zid`> specific apic

23:07 <zid`> keyboard sends irq 2 -> ioapic routes -> core 0 as interrupt 7 appears

23:07 <zid`> or such

23:07 <karenw> But the legacy pics are mapped to interrupts 32-47, then all masked off.

23:08 <karenw> I probabally don't need to map them anywhere, but earlier getting interrupts from them was progress

23:09 <heat> don't need to map the legacy pics yah

23:09 <zid`> can qemu dump your ioapic

23:09 <zid`> info pic has some stuff right?

23:09 <heat> yeah it can

23:10 <zid`> apparently my qemu emulates an ioapic with 24 external pins, and they're all routed to cpu 0

23:10 <zid`> I don't know what's connected to any of those pins though, haven't read the tables :P

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23:11 <karenw> heat: There was a comment on the wiki that you can get spurious legacy pic interrupts even when using the lapic.

23:11 <karenw> But that's probabally one of those things on ancient hardware

23:12 <karenw> And I don't suppport things pre-x64

23:12 <zid`> I don't have any raw ass machines that aren't under a hypervisor

23:13 <zid`> to dump my actual acpi tables from

23:13 <zid`> annoying

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23:13 <heat> you can get spurious pic interrupts yeah

23:13 <heat> but you can also get spurious interrupts in any case

23:13 <heat> that's something you _need_ to handle

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23:13 <karenw> Yeah, but if they come directly from the PIC, they need to not be mapped to <0x20

23:13 <zid`> cosmic ray interrupts

23:13 <karenw> Otherwise hilarity ensues

23:17 <karenw> If anything comes in on the vectors allocated for the legacy pics I just kprint a message and then send the legacy pics EOIs if they need them.

23:17 <karenw> Same if anything comes in via LINT0

23:17 <karenw> Just a different message and a lapic EOI

23:19 <zid`> I think we should have just chained another 8 more PICs on

23:19 <karenw> Oh god no

23:22 <zid`> good idea karenw, 12 more pics.

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23:31 <karenw> zid`: Just have pic0 have 8 more pics linked to all of it's lines

23:31 <karenw> 64 interrupts should be enough for anybody, right

23:32 <zid`> maybe we can make a superpic

23:32 <zid`> that has 128 lines, and we just chain two, for 255 interrupts

23:33 <karenw> Hardwire them to identiy map to vectors 0-255

23:33 <karenw> Hope you don't end up with a device mapped to an exception with error codes

23:35 <heat> karenw, yes but you don't actually need to assign vectors to the PIC

23:35 <heat> like, it's nice to remap them over the IO APIC space or something, but you really don't need to assign them vectors

23:35 <karenw> How would I know it's a spurious interrupt though?

23:36 <heat> it's a spurious interrupt if no interrupt handler claims the IRQ

23:36 <karenw> So... I'd poll the lapic and iopic and find they report no interrupt has happened?

23:36 <heat> no

23:37 <heat> generally what happens is: you see what irq number you got (from the vector, by reading a irq chip register, or whatever). you look for installed handlers. then call them one by one. if anyone claims the interrupt, it's not spurious. if someone claims the interrupt, it's spurious

23:37 <heat> s/someone/no one/

23:37 <bslsk05> <heat*> generally what happens is: you see what irq number you got (from the vector, by reading a irq chip register, or whatever). you look for installed handlers. then call them one by one. if anyone claims the interrupt, it's not spurious. if no one claims the interrupt, it's spurious

23:38 <heat> you'll EOI anyway

23:38 <karenw> Huh. Okay. Well... right now all interrupts are spurious by that logic. Except vector 254 (lapic timer)

23:39 <heat> also generally PCI interrupts are level triggered

23:39 <heat> so you really need to "claim the IRQ" in the device drivers, or you'll keep getting the IRQ even after EOI'ing in the LAPIC or wahtever

23:40 <karenw> Also: that helps explain why my laptop (running linux, not my OS) reports "No handler registered for interrupt {1,2,3}.55"

23:40 <karenw> During boot

23:40 <karenw> I assume that's linux saying "There was an interrupt on vector 55 on the non-boot processors, but no handler claimed it"

23:43 <heat> right

23:44 <karenw> This laptop has a lot of nonesense during boot. Like spec-violating ACPI tables and some other stuff. It's super cursed.

23:44 <zid`> > laptop

23:44 <zid`> found your problem

23:44 <zid`> laptop motherboard people are always nuts

23:44 <zid`> probably because they redo the shape of them every 20 seconds

23:45 <zid`> rather than sticking to a form factor and slowly incrementing the design, with the occasional socket wiring update

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23:47 <heat> spec-violating acpi tables? that's insanely common

23:48 <heat> IIRC all nvidia ACPI tables have a particular bug that ACPI interpreters just need to handle

23:49 <Ermine> hence acpica

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23:50 <Ermine> (conformant acpi tables would be a perk of coreboot imo)

23:52 <karenw> ACPI Warning: Time parameter 255 us > 100 us violating ACPI spec, please fix the firmware. (20240322/exsystem-141)

23:52 <karenw> 12 times every time I boot or resume from sleep

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23:54 <Ermine> "please fix the firmware" --- like user can fix it

23:56 <karenw> Lmao, try updating this piece of crap HP bios without a windows install to do it from

23:57 <kof673> <smashes corvette> in frustration

23:57 <heat> oh that's useless

23:57 <heat> i was going through acpica lately due to our dear maintaining going AWOL

23:57 <heat> they changed that warning into a warn once or whatever

23:58 <Ermine> > HP