<azonenberg>
oh soooo given that i'm in a (C/C++) exception handler routine on ARMv7-M
<azonenberg>
How do I return from the handler to an address other than the one I took to get there?
<Mutabah>
unwinding?
<zid>
C has exceptions?
<azonenberg>
sorry i mean a CPU exception handler
<Mutabah>
Actually, yeah - Do you mean a C++ exception? Or just a CPU exception being handled with C code
<Mutabah>
Ah, just reset the stack and jump elsewhere
<azonenberg>
tl;dr I need to catch a NMI, poke some register bits and set a global, and return to the instruction after the one that generated the fault
<zid>
fudge the pushed return
<azonenberg>
because apparently this chip throws a NMI when you have ECC faults
<azonenberg>
and i dont want to abort or reboot i just need to mark that chunk of data as unavailable and resume execution
<zid>
I'd hope so, else your ecc isn't doing its job :p
<azonenberg>
zid: welll
<azonenberg>
On STM32H7, it's sane
<azonenberg>
it sets a SFR bit and triggers a data fault (not a NMI)
<zid>
did you accidentally put it in one of those ionizing autoclave things
<azonenberg>
i.e. just an AMBA bus error
<azonenberg>
So when doing reads that I expect might fault I can just mask data faults, check the SFR for ECC error, then ignore the returned data in that situation
<azonenberg>
but on STM32L431 it NMI's so i have no choice but to recover in the exception handler
<azonenberg>
zid: NO this is power failure resilience
<azonenberg>
No*
<zid>
can you add that to my monitor
<azonenberg>
I built a sort of fuzzer where chip A is constantly resetting and power cycling chip B at random intervals from 500 to 1000 ms
<azonenberg>
while chip B is constantly writing test data to flash and doing internal consistency checks
<zid>
the psu in it is dying so it likes to randomly corrupt its instruction pointer into random bits of the rom
<zid>
so random menus will open
<azonenberg>
The goal is to build a config data storage where aborting at any time will result in either atomically rolling back to the old state or the new state being applied
<azonenberg>
The problem is that if you abort mid-write you sometimes get corrupted ECC state
<azonenberg>
that needs to not be fatal, it needs to treat the half-written data as corrupt and roll back to the previous version of the object
<azonenberg>
(this is basically a write-ahead log)
<azonenberg>
So yeah, NMI-ing when your WAL is corrupt is kinda contrary to the whole point of a WAL :p
<zid>
"Sprite is an exteprimental lime-like distributed soft drink system developed.."
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<geist>
ah yes sprite. i remember when that was a thing
<zid>
I like the heavily editorialized discontinuation paragraph
<zid>
"It wasn't a microkernel so it was too shit to bother with"
<geist>
heh yeah i saw that too
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* Ermine
gives gog a piece of cheese
* gog
is fascinated
* zid
flashes his armadillo
* gog
is indifferent
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<Ermine>
> fedora to replace power-profiles daemon with tuned
<Ermine>
tuned documentation: old one is on non-existent fedora wiki page, new one is wip
<netbsduser>
sprite, i know very little about sporit
<netbsduser>
i think i get it mixed up with spring in my memory
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<Ermine>
meanwhile C++ is going to get RCU
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<netbsduser>
Ermine: i saw they had a proposal for it
<netbsduser>
just the interfaces, i thought they looked geared to an epoch-based implementation rather than quiescent state based, but that's just my vague memory
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<heat>
yay LRU-2Q gives me some sort of scan resistence
<heat>
nice
<nikolapdp>
scan resistance'
<nikolapdp>
?
<heat>
yes
<heat>
basically it doesn't go completely tits up if you scan a big file or something
<zid>
I don't think you can stop terran scanning you
<zid>
hide your proxies better
<heat>
one has to note that dd by default uses 512 byte blocks which screws up the algorithm as the page cache thinks you're accessing the same page multiple times
<heat>
but with saner block sizes it works very well
<nikolapdp>
ooh
<nikolapdp>
i always put a 1mb bs for dd
<mjg>
scan resistance is for pussies
<mjg>
real programmers don't even cache stuff
<mjg>
you read something, keep it
<mjg>
any cache hit is a sign of userspace being slow
<mjg>
cmv
<heat>
caching is a sign of WEAKNESS
<heat>
you know what's really funny? no one can agree on how the active/inactive lists should be sized
<chiselfuse>
given system V abi with a processor supplement etc. why can't objdump show me the *effective* signature of a function. (ie based on the abi, how many args it seems to be taking and returning and of what sizes)
<zid>
how would it know?
<heat>
it could-ish if you analyze it
<zid>
what data is it supposed to look at?
<heat>
but e.g stuff like struct A {u64 a, b;} can be pushed as two args, so you're screwed there
<chiselfuse>
zid: by checking which registers it reads from without previously writing to and which offsets it tries to access from the previous stack frame
<zid>
huh? how would objdump know 'what registers it reads'?
<mjg>
heat: you waste time fucking with lru management and i'm literally faster not even trying
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<mjg>
me: 1 you: 0
<heat>
:(
<zid>
f: push rax; pop rbx; mov rcx, rbx; Is rax read?
<chiselfuse>
zid: if it does `push rdi` or `mov rax, rdi` without previously writing anything to rdi, it looks like it's reading rdi, since it's designated for an argument in the abi then i would consider it an argument
<zid>
okay, so now you're writing an emulator
<zid>
and solving the halting problem
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<zid>
have fun
<gog>
i'm halging the solving problem
<gog>
halting
<zid>
I am implementing the halting
<zid>
You're all going to die once I flip the switch.
<heat>
mjg, mon one has to wonder, does memory reclaim not affect performance on a loaded system?
<gog>
ugh god finally flip the switch already
<gog>
i'm ready now
<mjg>
what
<zid>
You'll never know if I do
<zid>
it won't help you
<mjg>
if you are near capacity buy more ram or rewrite in rust
<heat>
mjg, one has to assume the reclaim paths are ran "all the time" on a loaded system
<heat>
say you're running a big postgres instance
<mjg>
what do you mean by reclaim here
<mjg>
free some shit up and use for smoeting else?
<heat>
the codepaths responsible on a given kernel to get you to lotsfree
<mjg>
because if you do it at the last possible moment, not proactivel
<mjg>
proactively
<mjg>
that's a different between working or not working
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<mjg>
however, maintaing any form of recency tracking *does* impact perf
<mjg>
in some cases very poorly
<mjg>
globally locked lru requeueing every time being the poster child
<mjg>
erm, affects pretty bad so shit can perform poorly literally on that account
<mjg>
:>
<mjg>
you even got the linux people ranting about folio lru
<heat>
but does it not impact perf even without recency tracking?
<heat>
i guess if you're careful picking lotsfree you can somewhat alleviate this?
<mjg>
the very fact that you can reclaim something if there is no free memory?
<mjg>
it is not inherent
<mjg>
but most typical code adds some bullshit whic does not have tobe there
<mjg>
in some cases changes to facilitate this are not avoidable
<chiselfuse>
zid: why would it matter if rax is read in the function? it's not designated to an argument so if you rely on its state when the function begins isn't that non-determinism?
<zid>
I did wonder if you'd miss the point and nitpick after I wrote it, heh
<mjg>
example: suppose you want to keep negative name cache entries at bay
<mjg>
for that to happen you need a data structure to keep track of them
<mjg>
which you would not need otherwise
<chiselfuse>
zid: can you word your point instead because i don't understand what you're trying to say
<mjg>
so that's overhead to add/remove from it
<mjg>
and extra memory usage
<zid>
[23:25] <zid> okay, so now you're writing an emulator
<zid>
[23:25] <zid> and solving the halting problem
<zid>
Your method requires this, ignore rax.
<heat>
mjg, i dont see your point
<chiselfuse>
zid: without you being accurate to the abi i don't understand what to make of your example. assuming rax is designated for a first argument, you populate with it rbx and rcx. without in turn regarding for what either of those registers represent in the abi, i don't know how to try to interpret the signature of the function as (which i assume is what you want me to try to do with your example to fail so
<chiselfuse>
you can make a point, but again i can't because you're telling me to ignore the abi which is the whole point)
<zid>
sigh
<zid>
f: push rdi; pop rax; mov rcx, rdi
<zid>
is rdi used by this function
<chiselfuse>
zid: i'd say yes
<zid>
why do you say yes?
<zid>
Is it because you *ran the code in your head*?
<chiselfuse>
okay i see your point
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<heat>
basically what you're trying to do is called decompiling
<zid>
And that's (more or less) why you also need to solve the halting problem, I can write arbitrarily complex code and use the result to access registers
<chiselfuse>
i don't think it's decompiling. i'm trying to answer a question about the machine which turns out to be undecidable
<zid>
It's exactly what IDA has to do
<zid>
and it's why IDA costs thousands of dollars
<zid>
99% of what IDA does, is this
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<chiselfuse>
i don't get your last example though, it doesn't take any args and changes rsi and rax
<chiselfuse>
oh nvm
<zid>
which reg does it read from the stack? it depends if that big number is prime or not
<zid>
(should be rax*8 or whatever I guess)
<chiselfuse>
zid: yea but that big number is hardcoded, why didn't you make it so we got it as an arg instead
<zid>
I could call solve_the_lorentz_conjecture
<zid>
you keep missing the forest for the trees
<zid>
the point isn't I hardcoded a number
<zid>
it's that I can make *incredibly* complex math the barrier to knowing which register gets read
<chiselfuse>
you keep giving inaccurate examples and i'm not the smartest person :P
<zid>
They're accurate to the point, not accurate to weird conditions you add after
<zid>
"You can't know what registers a function touches, here's an example" "But rax isn't a parameter register!" "Okay *writes it to use a different reg, praying that one will pass muster*"
<zid>
If you can't prove it for rax, you can't prove it for rdi
<zid>
if you can't prove it for isprime, you can't prove it for the collatz conjecture
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