whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
<_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JoSmu
<_whitenotifier-1> [YoWASP/nextpnr] whitequark 511b8b0 - Update dependencies.
<d1b2> <Philpax> What are some interesting nmigen codebases to look at if I want to get familiar with nmigen "in the wild"? My interests lie in CPUs, if that helps
<_whitenotifier-1> [nmigen-yosys] jeremyherbert commented on issue #2: Setup on Intel Mac not working - https://git.io/JoS9w
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<d1b2> <Philpax> thanks! Had a quick skim and that's useful for getting the general feel. I'd also like to see some larger codebases, just to see what it's like to scale it up and how that interacts with Python
<dragonmux> oh, the other one that you might find interesting from us is https://github.com/DX-MON/iCEd-Salvador
<dragonmux> but that's fair regarding larger codebases
<tpw_rules> one neat "only in nMigen" thing is the special register address bus: there's a list of units and their registers, and python automatically generates optimal decoding logic and register layout
<tpw_rules> which is consistent between the gateware and the assembly
<dragonmux> iCEd Salvador is doing something quite similar for automaticaly generating addresses for things in the backing FRAM vs the runtime state
<tpw_rules> how much fram do you have?
<tpw_rules> it always seemed too expensive to me. also, do you know what happens to it during power loss?
<dragonmux> 8KiB, which for this project's needs is excessive.. £2.30 cost, so about the same as Flash but without the wear problem
<dragonmux> because it's Feroelectric, no data loss under power loss - it's equivilent to Flash but based off core memory significantly minaturised
<dragonmux> also, 10^12 guaranteed rewrite cycles
<tpw_rules> is it guaranteed to be atomic?
<dragonmux> per byte cell, yes
<tpw_rules> i knew those facts about it
<tpw_rules> but doesn't it involve destructive reads?
<dragonmux> not observably.. but probably under the hood
<dragonmux> the chip we picked uses SPI, so there's a controller in there smoothing things out for us
<tpw_rules> well that was one way it could not be atomic
<dragonmux> but, the protocol is set up so you can pull chip select low, send the write (after write enable) or read instruction, pick an address and immediately start clocking bytes in/out without setting a new address up, allowing you to rewrite the entire FRAM in 65568 cycles
<dragonmux> we would anticipate there necessarily being some extra work required on the read side if reads were distructive, and on the write if they had to go through some kind of buffering
<dragonmux> which is why things like Flash has pages, and the need to write a page at a time and wait for a bit in the status register to clear
<tpw_rules> i guess i just don't trust it. or haven't seen any proof
<dragonmux> well, consider this: FRAM is good enough that there are well prooven MSP430's running off the stuff
<dragonmux> not just using it as EEPROM replacement, but literally as system memory and program memory
<dragonmux> at least in iCEd Salvador's case, if it works, that's fantastic.. if it turns out to be buggy and a bad idea, we can replace it with Flash after introduction of write timers and a writeback cache (and some very tear-y sad faces along the way), so it's no big loss
<d1b2> <Darius> I think there are also hybrid FRAM/Flash chips where they use the FRAM to hold the wear levelling table etc
<tpw_rules> there's also the EERAM
<dragonmux> haven't heard of EERAM before
<dragonmux> ah, SRAM with Flash bolted onto it (ish)
<d1b2> <Darius> EERAM?
<d1b2> <Darius> ah OK
<tpw_rules> yeah it's SRAM that has an (outboard) capacitor to copy to EEPROM on power loss
<d1b2> <Darius> "Eeram ( transl. Moisture) is a 2009 Indian Tamil-language supernatural crime thriller film written and directed by Arivazhagan in his directorial debut ..."
<d1b2> <Darius> thanks Google! 😄
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<_whitenotifier-1> [nmigen] fnsangiul opened issue #642: Using nMigen with YoWASP in Windows - https://git.io/Jo9Ni
<_whitenotifier-1> [nmigen-yosys] whitequark commented on issue #2: Setup on Intel Mac not working - https://git.io/JoHUc
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<_whitenotifier-1> [nmigen-yosys] jeremyherbert commented on issue #2: Setup on Intel Mac not working - https://git.io/JoQft
<_whitenotifier-1> [nmigen-yosys] jeremyherbert closed issue #2: Setup on Intel Mac not working - https://git.io/JogwJ
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<kaucasus> Is there an elegant way to assign operate on a record with subrecords? With that I mean, is it possible to do something like `m.d.comb += self.o_data.eq(MyRec(SubRec1(0),SubRec2(1)))` Or are you basically forced to do `m.d.comb += [self.o_data.subrec1.val1.eq(0),self.o_data.subrec2.val1.eq(1)]`
<vup> kaucasus: if the layout of MyRec is just SubRec1 and then SubRec2 you can do `self.o_data.eq(Cat(Const(0, $SubRec1Bits), Const(1, $SubRec2Bits))
<kaucasus> vup: Thanks! That works, but I just realised that it's actually more difficult for me to actually follow which signal is which then, so I guess the extra verbosity works better for my brain
<kaucasus> Hmmm is there a way to test internal state of a (sub)module? Currently trying to do the following: `self.dut = MyModule()` in the testcase and `yield self.dut.submodules.mysubmodule.o_out` in the testbench process, but Python complains that `AttributeError: 'MyModule' object has no attribute 'submodules'`
<kaucasus> which is weird, since I explicitly named "mysubmodule" in the MyModule elaborate function, and it shows up under that name on the vcd file
<miek> submodules is an attribute of the Module you create in elaborate, it's not an attribute of MyModule
<kaucasus> ah, makes sense! But is there anyway to access it then from a higher module for the test?
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