whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
<_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/J6a46
<_whitenotifier-1> [YoWASP/nextpnr] whitequark a8b5888 - Update dependencies.
<_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/J6VYw
<_whitenotifier-1> [YoWASP/yosys] whitequark b32321f - Update dependencies.
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<kaucasus> Is there an easy way to memory-map IO for a board with the built-in Memory() module?
<Sarayan> memory-mapped i/o is not memory
<DX-MON> though you can map Memory() to addresses in your processor as SRAM by comparing high address bits and feeding the read_port() and write_port() address signals the low bits
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<dragonmux> MMIO is acomplished using CSRs though
<kaucasus> In the future we would indeed like to use CSRs, but it's just a proof of concept rn. We basically wanted to act like if buttons/leds of our board is just the same as a lw/sw instruction for any data
<kaucasus> (Making a risc-v processor, but I think you folks already assumed that one :P)
<dragonmux> that is literally the CSR process, yes - you compare a memory address vs what's on the bus, and if it matches, then the data on the bus is routed to your register (or the reigster routed to the data lines of the bus) based on the bus protocol. The bits of that register then drive and are driven by your buttons/LEDs
<dragonmux> CSR here doesn't refer to RISC-V CSRs which are their own.. other.. thing
<kaucasus> ohhh okay! So in memory mapped io the memory/register made with Memory() and the register actually driving your leds/buttons are two different registers who always have the same value
<kaucasus> I feel like I'm misunderstanding something right, is nmigen/yosys then smart enough to not actually generate/synthesize the redundant register?
<kaucasus> Currently in our elaborate we just do `m.submodules.led_port = led_port = self.memory.read_port()` and later `m.d.comb += [led_port.addr.eq(MEM_MAPPED_IO_LOC), self.o_leds.eq(led_port.data)]` But I don't think that's what you mean?
<Sarayan> you want a register with backing storage in your address map?
<Sarayan> the trick is, if your register is part of a memory block, you can't have a direct access to it, you have to read the memory to get the value, and that's usually not what you want
<Sarayan> the point of registers usually being fast, parallel, direct access
<kaucasus> Yeah we don't really *want* a register with backing storage in the address map and yeah that's the problem we kinda wanted to solve of it being part of the memory block
<kaucasus> Though I guess it doesn't matter that our leds and buttons don't have fast access since they're only used in the core itself and it's not like it needs it's own clock or any weird stuff like that
<kaucasus> (but later for a UART that might be a problem)
<Sarayan> the address *map* is not the memory
<Sarayan> the memory includes an address decoding, but if you have an address map you have to have some kind of chip select too
<Sarayan> and the matches() you do for your register decoding is not going to be signigicantly slower than your chip select decode
<dragonmux> yeah, what we're saying is that Memory() is only good for SRAM blocks mapped into your processor, for what you're doing you want to use the Wishbone CSR pattern
<dragonmux> in this pattern you define a Signal(8) or w/e the width of the bus is, you decode the address on the processor's bus, resulting in a "matches" signal and when it matches you either assert your signal onto the bus, or assert the bus contents onto the signal in the sync domain
<dragonmux> you then have bits you can drive the LEDs with (`m.d.comb += self.o_leds.eq(ledReg)`) and that's all there is to it
<dragonmux> trying to involve Memory as opposed to a nmigen-soc MemoryMap is over-complicating things
<dragonmux> it's not for the same bus as you're using but this is the kind of thing I'm getting at: https://github.com/DX-MON/OPLSniffer/blob/f2edd8aa20bf8b4a95ddae74eeaa196bfeedc10b/gateware/sniffer/gpio/__init__.py#L5
<dragonmux> this happens to create a GPIO peripheral with 3 MMIO addresses, but I think you get the idea
<kaucasus> thanks folks! I'm gonna read all those, they look very helpful
<dragonmux> https://github.com/lethalbit/squishy/blob/main/software/squishy/gateware/core/interface/scsi.py contains an example of using the WishboneCSRBridge to help bring it out the abstract into the concrete
<dragonmux> and https://github.com/lethalbit/squishy/blob/main/software/squishy/gateware/core/__init__.py contains the example of how to hook controllers and peripherals up to that bus
<dragonmux> (in that particular project it happens that every periphal is also a controller able to make requests on the bus, which is why each peripheral has a self.ctl_bus that is added to the arbiter as well as a self.bus that is added to the decoder)
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<FL4SHK> How do I use a platform's `connectors`?
<FL4SHK> Such as the PMODs on the Arty A7
<miek> you add a Resource to the platform (that references pins on the connector), then request & use that resource
<FL4SHK> The platform is already defined
<FL4SHK> I'm using nmigen_boards
<miek> that's fine, you can still add another resource to it on the fly
<FL4SHK> Ah, I see.
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