whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
Degi_ has joined #nmigen
Degi has quit [Ping timeout: 252 seconds]
Degi_ is now known as Degi
benreynwar_ has joined #nmigen
benreynwar_ is now known as benreynwar
mwbrown has joined #nmigen
cr1901 has quit [Ping timeout: 245 seconds]
cr1901 has joined #nmigen
kaucasus has joined #nmigen
FL4SHK has quit [Ping timeout: 260 seconds]
FL4SHK has joined #nmigen
zignig has joined #nmigen
zignig has quit [Client Quit]
zignig has joined #nmigen
kaucasus has quit [Quit: Client closed]
k-haze has joined #nmigen
<k-haze> Hello, is there any way to call verilog code from nmigen? (access to PLL is needed)
<tpw_rules> k-haze: yes, use an Instance: https://lab.ktemkin.com/post/nmigen-instance/
<k-haze> thank you!
<FL4SHK> How does nMigen play with stuff like Vivado's Zynq business?
<vup> anuejn and me are using it to great success (https://github.com/apertus-open-source-cinema/naps)
<FL4SHK> vup: that's for Zynq?
<vup> parts of it, yes
<FL4SHK> Neat.
<FL4SHK> I'll bookmark this.
<dragonmux> FL4SHK: we've been working on Zynq SoC and Ultrascale+ SoC support over at https://github.com/shrine-maiden-heavy-industries/arachne
lf has quit [Ping timeout: 265 seconds]
lf_ has joined #nmigen
k-haze has quit [Ping timeout: 264 seconds]