whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
<_whitenotifier-d> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/f613a208028f...0db9acb1b7af
<_whitenotifier-d> [YoWASP/yosys] whitequark 0db9acb - Update dependencies.
<d1b2> <Chuck> so, if you want to have a sequence of bit values sent to a signal port, what is the syntax?
<d1b2> <Chuck> If I say num = Signal[7] and seq = 0xb110011, 0xb00110011, ... 0xb00000] and have
<d1b2> <Chuck> num.eq(seq[index]) that doesn't work
<tpw_rules> seq needs to be an Array if you want to index with a Value
<mwk> also it's 0b<bits>, bot 0xb<bits>
<mwk> *not
<d1b2> <Chuck> if I make num just a python variable then num = (num + 1) % 8
<d1b2> <Chuck> sorry yes its 0b<bits> bad typo and seq is an array
<tpw_rules> i mean the nmigen type
<d1b2> <Chuck> Ahhh
<d1b2> <Chuck> gotcha
<d1b2> <Chuck> I'm trying to create an array of a static values that are fed to signal lines as part of a protocol sequence. If I were writing this in Python it would be : foo = [0b001, 0b002, 0b003, ... 0bxxx] for (x in foo): signal_lines = x
<d1b2> <Chuck> But doing that in *Migen is eluding me
<tpw_rules> well you have to have a clock to advance the counter
<d1b2> <TiltMeSenpai> yeah you get to do it the good old fashioned way, with indices and stuff
<d1b2> <Chuck> Yes, but this: [ index.eq(index+1), if (index > LEN, index.eq(0)), signal_lines.eq(foo[index]) ] Doesn't compile at all
<jevinskie[m]> index needs to be a Signal too
<tiltmesenpai[m]> also, nmigen isn't just python, your gateware is more of a data structure manipulated using python code
<jevinskie[m]> And foo must be an array as well. Slicing only works using compile-time constants on Signals
<jevinskie[m]> Array with a capital A, the *migen class
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<d1b2> <Chuck> Yup jevenskie: I got that, earlier I was complaining about initializing an Array with constants. So something like: foo = Array(Range(5)) bus = Signal(8) ?? foo = [c1, c2, c3, c4, ... c8] ?? # (yes I know 'cx' isn't a constant, imagine a # constant like 0b11000 there)
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<d1b2> <Chuck> Then with index = Signal(3) sync += [ index.eq(index + 1), bus.eq(foo[index]) ] As the part that bursts out the prefix header
<d1b2> <Chuck> anyway, none of that works in a way that I understand it yet. I can use a Case() statement which seems gross but it seems to do what I want. I'm more trying to understand how to write code that the synthesizer can infer minimum hardware for.
<d1b2> <Chuck> Sorry to the folks on irc I know this looks pretty borked.
<DX-MON|> If we recall correctly, it's Array(Signal(8), range(8)), or alternatively build a Python array using Const() (so the constants get widths and a shape defined) and hand that array to Array to convert it
DX-MON| is now known as dragonmux
<dragonmux> because you need to not just tell it how many Array elements you want, but you have to define their shape
<dragonmux> (how wide they are)
<d1b2> <Chuck> Interesting, okay can try some of those.
<d1b2> <dragonmux> ah, right.. Array's initialisation parameter is an iterable
<d1b2> <dragonmux> so it's the latter
<d1b2> <dragonmux> build your Python list/tuple (preferably tuple tbh) using Const and define all the constants and then pass that to Array to *Migen-ify it
<d1b2> <Chuck> hmmmm
<d1b2> <Chuck> That seems to work
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<d1b2> <dub_dub_11> Also depending on how the protocol works, you may want to consider using FSM()
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