whitequark changed the topic of #nmigen to: nMigen hardware description language ยท code https://github.com/nmigen ยท logs https://libera.irclog.whitequark.org/nmigen
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<_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/ยฑ1] https://git.io/JPBi9
<_whitenotifier-1> [YoWASP/yosys] whitequark 37ce66c - Update dependencies.
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<d1b2> <dbosky> Quick question - does nMigen support importing RTL? I'm looking for a tool (preferably something in Python) that can automate/simplify connections between different RTL modules and then spit out a top verilog/sv file where everything is nicely connected? This is to replace ton of generate statements I have currently in that top file.
<tpw_rules> is this what you mean? https://lab.ktemkin.com/post/nmigen-instance/
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<d1b2> <dbosky> Good bot.
<tpw_rules> nobody involved is a bot
<d1b2> <TheManiacalLemon> (on Discord the IRC connector makes everyone show up as a bot)
<d1b2> <TheManiacalLemon> Just FYI dbosky ๐Ÿ˜„
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<d1b2> <dbosky> @TheManiacalLemon haha ok, good to know ๐Ÿ™‚
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<d1b2> <dbosky> I have another question - is there an easy way to create a SV like interface/modport to simplify connections between modules? I don't want to connect all AXI signals individually every time.
<whitequark> you can currently use Record, though it's flawed and we're going to replace it eventually
<cr1901> Doesn't scale past medium-small designs, but I just eat the time cost of having to route connections into modules.
<d1b2> <TheManiacalLemon> Playing around with Instance... is there a way within the nMigen tooling to simulate an Instance, or do I need to export the whole thing to Verilog and then feed it into a third party simulator? I implemented a counter in both Verilog and nMigen sync domain, put both in the self.ports array... only the nMigen counter variable is showing up
<d1b2> <TheManiacalLemon> (in the vcd, that is). I wonder if there's a way to use cxxrtl to do it but I'm unfamiliar with using that particular simulator
<mwk> there is, but I'm not sure if there's a convenient way to use it
<mwk> hold on...
<mwk> generally an Instance is a Fragment in nmigen, ie. more or less an elaborated module, with the special handling that replaces it with an external cell instantiation when emitted to RTLIL
<mwk> the contents of this fragment are normally empty, which means the Instance just effectively disappears in pysim
<d1b2> <TheManiacalLemon> Yeah, I had a feeling the issue was that the backend is only simulating the python code, and not anything analyzed by yos
<d1b2> <TheManiacalLemon> *yosys
<mwk> but, you can add actual behavioral statements to the Instance, which will be used for simulation (nmigen.hdl.mem.* do this internally), and ignored when emitting RTLIL
<mwk> I'm just not yet sure if there's a pretty interface for that...
<whitequark> there isn't
<mwk> of course, the whole thing requires your instance to be synthesizable in the first place, so would only work for things like DSP cells
<whitequark> it's kind of an awkward part of the simulator
<mwk> you may want to investigate cxxrtl instead
<mwk> rewriting whatever cell you have in nmigen when you already have it in Verilog is not exactly fun
<d1b2> <TheManiacalLemon> Exactly, I was mostly looking for a stopgap solution for my project while certain components don't exist yet in nMigen code. Once they're converted then it's a non issue
<mwk> what *do* they exist as?
<d1b2> <TheManiacalLemon> Just verilog files
<d1b2> <TheManiacalLemon> I think cxxrtl is probably the best solution as long as it can read verilog files (seems it can since yosys can parse verilog?)
<d1b2> <TheManiacalLemon> Just need to do some looking on my end to figure out how to use it
<mwk> yeah, I do recommend cxxrtl in this case
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