00:21 <_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JohUU

00:21 <_whitenotifier-1> [YoWASP/nextpnr] whitequark 1d9eaaa - Update dependencies.

01:00 <_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Joh8h

01:01 <_whitenotifier-1> [YoWASP/yosys] whitequark 870ba47 - Update dependencies.

01:58 <d1b2> <Greg> Is there a recommended way to bring signals out to a top-level verilog module generated from an nmigen module? This is how I've done it so far, which is working. But not sure if it's the easiest way. https://github.com/butterstick-fpga/butterstick-bootloader/blob/main/gateware/rtl/eptri.py#L110-L121

03:06 <tpw_rules> i would use `dir` instead of `vars` personally but i don't think it matters in the grand scheme of things

03:18 <d1b2> <Greg> That's easy to change, thanks. I guess specifically the way I'm using _lhs_signals() to collect and pass ports into nmigen.back.verilog.convert feels wrong, like there should be a nicer way.

03:20 <tpw_rules> i don't understand why you aren't just using the ports themselves

03:26 <d1b2> <Greg> This is why I'm asking. I think I hit problems trying to use the ports directly.

03:27 <d1b2> <Greg> IIRC likely due to me wanting to pass Records of signals through. like the ulpi and wishbone bus.

03:29 <tpw_rules> i guess now that i look at my own code what i have is a wrapper module that just names all the verilog ports

03:30 <tpw_rules> then the body is just instantiating the main module and combinatorially connecting everything up, with the `dir` loop to collect it all for the verilog generation

03:30 <tpw_rules> that's probably clearest, if less easy

03:32 <d1b2> <Greg> I've probably spent longer trying to automatically collect all the signals, rather than just manually write them all out.

03:32 <tpw_rules> isn't that always the case ;)

06:30 <d1b2> <zyp> https://github.com/orbcode/orbtrace/blob/main/orbtrace/nmigen_glue/wrapper.py

06:40 <d1b2> <Greg> I have taken a look at your wrapper awhile ago. Your implementation does appear a bit cleaner. Might port my code over to the way you're doing it.