whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
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<FL4SHK> How do you simulate in nmigen?
<FL4SHK> So far, I've been doing just formal actually running in an FPGA.
<FL4SHK> I'll look up the guide
<doinkmaster420> you can find some cool tricks in the nmigen tests or glasgow too
<FL4SHK> Cool, thanks.
<dragonmux> shows how to do some more complex simulation work and set up dummy platforms, etc
<FL4SHK> dragonmux: thank
<dragonmux> please don't hesitate to ask if you have any questions about what's going on in our sim stuff
<FL4SHK> Sure thing.
<FL4SHK> So do I use Python `if` statements instead of `with m.If(...)` for simulation?
<dragonmux> depends on the context.. if you're constructing something inside an Elaboratable that you want making decisions in gateware, then it's `with m.If()` as normal
<FL4SHK> The context is within the `process` function
<dragonmux> if you're wanting to direct sim based on what you're seeing happen, then it's Python `if`
<FL4SHK> Right, that's what I was getting at.
<dragonmux> `yield dut.signal` will give you the current value of the signal as a number you can work with and manipulate
<dragonmux> `yield dut.signal.eq(value)` will set the signal to the value given for the next cycle (a cycle is any `yield` with nothing to the right
<FL4SHK> I see.
<FL4SHK> I didn't realize you could, in nMigen, slice into an expression that's not a signal
<FL4SHK> slicing into an rvalue is sorely missing from VHDL and SV.
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<_whitenotifier-1> [nmigen] lethalbit opened pull request #644: vendor.openlane: OpenLANE ASIC Platform - https://git.io/JiZXy
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