00:20 <_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JoCbz

00:20 <_whitenotifier-1> [YoWASP/nextpnr] whitequark fc21323 - Update dependencies.

08:36 <Sarayan> nmigen is hard, let's go shopping

08:36 <Sarayan> File "/home/galibert/.local/lib/python3.9/site-packages/nmigen/hdl/ir.py", line 396, in add_defs

08:36 <Sarayan> AssertionError

08:36 <Sarayan> assert defs[sig] is self

08:36 <Sarayan> (makes me go muh?)

08:37 <whitequark> https://github.com/nmigen/nmigen/issues/398, perhaps?

08:44 <Sarayan> maybe, except I have no pins, I generate an instance of a thing that's two 32 bit ports, one from hps to fpga and one the other way around, and I connect them together

08:46 <Sarayan> og.kervella.org/mister-tests.zip

08:51 <Sarayan> maybe it's too simple, and nmigen hasn't encountered that kind of case yet

08:52 <whitequark> you're assigning to an output

08:53 <Sarayan> I crossed the streams?

08:53 <whitequark> you have: m.d.comb += hps_gp.o_gp_out.eq(hps_gp.i_gp_in)

08:54 <whitequark> you probably want: m.d.comb += hps_gp.i_gp_in.eq(hps_gp.o_gp_out)

08:54 <whitequark> or, hm

08:54 <Sarayan> it probably should be o_gp_in

08:54 <whitequark> yes

08:57 <Sarayan> it's compiling, the .v looks correct

09:01 <Sarayan> interestingly the rbf is not working

09:05 <Sarayan> there are no routes, wow

09:05 <Sarayan> I guess I've hit a limit of quartus there

09:05 <_whitenotifier-1> [nmigen-yosys] jeremyherbert opened issue #2: Setup on Intel Mac not working - https://git.io/JogwJ

09:08 <Sarayan> gonna have to register it to have quartus do something sane

09:57 <Sarayan> impressive, I can't get quartus to cope with the nmigen-generated code

09:59 <Sarayan> difficulty is that once I add a register th code is too complex to follow, let's see if I can remove the register from the working verilog version

10:09 <Sarayan> interesting, the verilog version works with register removed

10:12 <Sarayan> ohhh, looks like I inverted input and output in the instance, that would do it

10:14 <Sarayan> and when I fix that it works, yeepee!

10:14 <Sarayan> Instances are the easy asm() of nmigen :-)

10:27 <Sarayan> ok, now that I have that simple code working I can try to create a mistral-based chain to generate the rbf

11:56 <_whitenotifier-1> [nmigen-yosys] whitequark commented on issue #2: Setup on Intel Mac not working - https://git.io/Jow0d

12:23 <FL4SHK> Found an issue with overloading `__setattr__` for a class derived from `ValueCastable`.

12:26 <FL4SHK> shoot, something is going on with my network connection?

12:27 <FL4SHK> SSHing is doing something strange

12:27 <FL4SHK> it disconnects for some reason.

12:27 <FL4SHK> Well, maybe not disconnecting, but I digress

13:01 <FL4SHK> Are there any tips for creating a class that both overrides `__setattr__` and derives from `ValueCastable`?

13:02 <FL4SHK> I was seeing strange behavior.

13:03 <FL4SHK> I was able to go without the `__setattr__` override for my application.

15:55 <FL4SHK> Seems I'm getting an error upon trying to do some formal verification.

16:07 <FL4SHK> It's a yosys error in particular, so I've asked in #yosys

17:57 <FL4SHK> Got everything resolved.

17:57 <FL4SHK> My long divider works.