00:19 <_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JrQdC

00:19 <_whitenotifier-1> [YoWASP/nextpnr] whitequark 58d2b4d - Update dependencies.

00:54 <_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jr7IT

00:54 <_whitenotifier-1> [YoWASP/yosys] whitequark f868050 - Update dependencies.

02:05 <d1b2> <Philpax> not to dwell on the departed but I really do want to see libre-soc succeed, but interpersonal skills are an important part of that :/

02:05 <d1b2> <Philpax> ah well, hopefully he can do what he needs to do

07:56 <_whitenotifier-1> [nmigen] hansfbaier opened pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/Jrxbl

07:59 <_whitenotifier-1> [nmigen] hansfbaier commented on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JrxjO

08:53 <_whitenotifier-1> [nmigen] hansfbaier edited pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/Jrxbl

10:07 <_whitenotifier-1> [nmigen-boards] rroohhh reviewed pull request #185 commit - https://git.io/JoeOA

10:08 <_whitenotifier-1> [nmigen] whitequark commented on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JoeGv

12:05 <_whitenotifier-1> [nmigen] hansfbaier commented on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JoJGn

12:41 <_whitenotifier-1> [nmigen] whitequark commented on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JoULG

12:41 <_whitenotifier-1> [nmigen] whitequark edited a comment on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JoULG

12:44 <_whitenotifier-1> [nmigen] hansfbaier commented on pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/JoUOB

12:45 <_whitenotifier-1> [nmigen] hansfbaier closed pull request #640: fix reversed bit order in PriorityEncoder - https://git.io/Jrxbl

13:17 <FL4SHK> Any particular reason that some of my ports specified with `generate -t verilog` don't show up?

13:17 <whitequark> do you have an MCVE?

13:18 <FL4SHK> What's MVCE?

13:18 <whitequark> https://stackoverflow.com/help/minimal-reproducible-example

13:18 <FL4SHK> Oh, that.

13:19 <FL4SHK> I'll have to try to produce one.

13:42 <FL4SHK> Does nMigen do anything weird if you have a module that doesn't use `m.d.sync`?

13:43 <dragonmux> no, it gracefully handles that

13:43 <FL4SHK> Good to hear.

13:58 <FL4SHK> the issue I thought there was is actually not an issue

13:58 <FL4SHK> I think, let me double check.

14:13 <FL4SHK> Well, new problem. Somehow one of my signals is being driven from `d.comb` when I don't think I ever drove it from `d.comb`

14:19 <FL4SHK> Ah, found the solution.

14:42 <_whitenotifier-1> [nmigen] H-S-S-11 opened issue #641: Attributes are not properly applied to IBUFDS (and possibly other primitives) in Xilinx platform - https://git.io/JoIRh

14:42 <_whitenotifier-1> [nmigen] H-S-S-11 edited issue #641: Attributes are not properly applied to IBUFDS (and possibly other primitives) in Xilinx platform - https://git.io/JoIRh