<lkcl>
286Tech: i totally get this. there was a beautiful implementation of an LRU algorithm in VHDL as part of microwatt. converting it to nmigen was... awkward.
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<lkcl>
in order to avoid the (costly, serious) mistake of thinking, "assigning nmigen HDL AST expressions to a python variable will make them actual HDL assignments"
<lkcl>
i had to create temporary signals *receiving* the *result* of those nmigen HDL AST expression fragments, and using the *temporary signal* in the next iteration of the loop.
<lkcl>
this of course completely Messed with the HDL itself and made it rather less easy to read that the original VHDL.
<lkcl>
got the job done though
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<d1b2>
<286Tech> Yeah, I think it's easier if I just rethink how the code should work, rather than emulate VHDL variables or Verilog blocking assignments.
<d1b2>
<286Tech> In my case it shouldn't be too difficult (but I haven't read all the code yet)
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