whitequark changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://libera.irclog.whitequark.org/nmigen
<_whitenotifier-d> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JuBss
<_whitenotifier-d> [YoWASP/nextpnr] whitequark 7cf9f86 - Update dependencies.
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<d1b2> <286Tech> Are blocking assignments supported in nMigen? Or is there an equivalent to a VHDL variable?
<d1b2> <286Tech> I couldn't find anything related to it, so I suppose not, but I'd rather ask and be sure.
<d1b2> <dub_dub_11> Signal assignments are either combinatorial or sequential
<d1b2> <286Tech> Ok, thanks.
<d1b2> <286Tech> Guess I have to rewrite the logic then.
<Chips4Makers[m]> @286Tech I think nmigen assignments are more like VHDL blocking assignments. It allows things like:
<Chips4Makers[m]> m.d.comb += sig.eq(sig2)
<Chips4Makers[m]> * @286Tech I think nmigen assignments are more like VHDL blocking assignments. It allows things like:... (full message at https://libera.ems.host/_matrix/media/r0/download/libera.chat/d5c404b7cf8d998a5fb5e109c4609d6b0b543981)
<lkcl> 286Tech: i totally get this. there was a beautiful implementation of an LRU algorithm in VHDL as part of microwatt. converting it to nmigen was... awkward.
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<lkcl> in order to avoid the (costly, serious) mistake of thinking, "assigning nmigen HDL AST expressions to a python variable will make them actual HDL assignments"
<lkcl> i had to create temporary signals *receiving* the *result* of those nmigen HDL AST expression fragments, and using the *temporary signal* in the next iteration of the loop.
<lkcl> this of course completely Messed with the HDL itself and made it rather less easy to read that the original VHDL.
<lkcl> got the job done though
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<d1b2> <286Tech> Yeah, I think it's easier if I just rethink how the code should work, rather than emulate VHDL variables or Verilog blocking assignments.
<d1b2> <286Tech> In my case it shouldn't be too difficult (but I haven't read all the code yet)
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