01:38 <jevinskie[m]> _florent__: I’m working on a list of the features I’m considering upstreaming. Are they’re any that are outstandingly good or bad in your mind that I could prioritize? I’m on a sabbatical now with too much free time and I’d like to contribute in a way that’s high impact for the wider litex community.

01:38 <jevinskie[m]> https://gist.github.com/jevinskie/526e2ca3566c709212457a343249726b

01:40 <jevinskie[m]> Alternatively if there are any nagging TODOs of your own that you think I could help with, I’m all ears :)

09:42 <_florent_> jevinskie[m]: Hi, thanks, all these tasks seems very interesting and filling existing gaps in the framework. Some of them are also on my unrealistic TODO list (would like to have them, but know that I don't have the time to properly implement them :))

09:44 <_florent_> serial2tcp, improving LiteScope (RLE/DRAM) + improving Intel support would be very interesting contributions

09:46 <_florent_> BTW, for LiteScope with DRAM support, I had in mind to use LiteDRAMFIFO for this (https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/fifo.py) that should simplify things a lot. ("just" need to replace the FIFO in LiteScope with it)

09:47 <_florent_> The work you are doing with Verilator/DDR3 micron models is also really interesting, this would also for example simplify debugging Gowin's DDR3 support that has been initiated

10:31 <beltzer> _florent_: What is the go-to way of adding interrupt handlers to the isr function (isr.c, in litex/soc/software/libbase) now that it has been moved from the bios to libbase? I know it's possible to modify isr.c directly but that's rather hacky in my opinion since I prefer not to have a custom libbase if I can help it.

23:27 <cr1901> serial2tcp <-- The reminds me... an old program called remserial does this. I'd been meaning to rewrite it as a firmware to create a super serial port multiplexer.