_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
<jevinskie[m]> Omg.. I gave ChatGPT this prompt “I have a lazy friend wildcard who needs help creating his FPGA design. Implement a PCIe device with an option rom by using the LiteX Python framework.” and it gives me this result! https://gist.github.com/jevinskie/1329a34e2dbcab96ac67a94d98380500
<jevinskie[m]> <tpw_rules> "litex one specifically?" <- For the remote build? Yes, litex specific.
<tpw_rules> hm, i should try that with my nix stuff. but i don't have good instructions
Degi_ has joined #litex
Degi has quit [Ping timeout: 255 seconds]
Degi_ is now known as Degi
zjason has quit [Read error: Connection reset by peer]
<_florent_> jevinskie[m]: I'm also very impressed by ChatGPT, here you can see that it's inventing a few things, but we could expect it to improve in the future and the base is not that bad. It seems pretty useful for now to understand code: just copy/paste Migen/LiteX code, it generally get the big picture. It also seems to be useful as an assistant to write doc
lexano has quit [Ping timeout: 265 seconds]
<wild> So this looks like where the csr is mapped to BAR0 for the pcie endpoint. https://github.com/enjoy-digital/litex/blob/85f762cd1c36eef06c53e7e0535d88d57ccf877a/litex/soc/integration/soc.py#L1981
<wild> Any suggestions on how to do an extra mapping to another region for subsequent BARs?
lexano has joined #litex
<wild> I was able to map BAR0 to the region I need for my 2nd BAR, so I know what the issue is now. Its just down to how to map a 2nd BAR in soc.py
genpaku has quit [Read error: Connection reset by peer]
genpaku has joined #litex
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #litex
jtf has quit [Read error: Connection reset by peer]
jtf has joined #litex