_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> _florent_: i use liteeth in software mode (soc.add_ethernet()). i have the impression the sometimes the packet content changes while i'm processing it. i basically use udp.c, so ethmac_sram_writer_ev_pending_write(ETHMAC_EV_SRAM_WRITER) after process_frame()
<sensille> do you think that is a possible liteeth issue? or am i just doing something wrong in software?
<sensille> is my assumption correct that ...(ETHMAC_EV_SRAM_WRITER) makes the slot available again to the mac?
<sensille> it might take 10s of millions of packets to happen
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