<MoeIcenowy>
somlo: I am only talking about the hardware port, which is "the actual hardware"
<MoeIcenowy>
I know about the way Rocket DRAM port works
<MoeIcenowy>
the "actual hardware" decides how wide LiteDRAM native port is
<MoeIcenowy>
for 7-series with DDR3, the LiteDRAM native port width is the DRAM bus width * 8
<MoeIcenowy>
the DRAM bus width is the number of DQ lines
<MoeIcenowy>
for dual rank, it's not related to DRAM bus width, but it's adding another group of DRAM chips that share most signal ipns
<MoeIcenowy>
pins *
<MoeIcenowy>
the only pins related to dual rank here is ~CS, CKE, CLK_{p,n} and ODT
<MoeIcenowy>
you can see the platform definition of STLV7325, it's currently configured as 64-bit width with single rank, the dual rank pins are comments
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<_florent_>
somlo: Switching to dual rank should not increase the controller's data_width, it should only affect the addressable size (and internally the doubling the number of banks).
<_florent_>
somlo: If you confirm you see the data_width increasing, I would need to have a look because this is not expected
<_florent_>
somlo: BTW, for now LiteX we are limiting the mapped DRAM region to 1GB in the SoC. The reason is that we are limited to 4GB with a 32-bit bus and would need to re-arrange some internal mapping to allow more. We could also probably increase address width with 64-bit processors and remove this limitation.
<_florent_>
somlo: That's probably not that complex to do, but still needs to be done :)
<somlo>
and `memory_region,main_ram,0x80000000,2147483648,cached` in csr.csv, which is 2GB unless I screwed up my arithmetic :)
<somlo>
btw I ordered a MT8KTF51264HZ-1G9 so once it shows up I can run actual tests (and, with any luck, invest some time in understanding LiteDRAM a bit better :)
<somlo>
overall, I'm *very* interested in supporting 2GB+ main_ram (I really want to run a full yosys/trellis/nextpnr flow to build ecp5 bitstream for litex+rocket, *on* litex+rocket :)
<MoeIcenowy>
maybe I should also try to buy a bigger SODIMM for my STLV7325 ;-)
<MoeIcenowy>
somlo: the DRAM size is calculated with DQ width, rank number, bank group number (not available for DDR3), bank number (fixed at 8 for DDR3), column address width, row address width
<MoeIcenowy>
column address width and row address width is decided by the chip selected in litex_boards.targets.XXX
<somlo>
huh, maybe I should try and get an STLV7325 board
<MoeIcenowy>
somlo: you do not need to get one
<MoeIcenowy>
VC707 is better than it on everything.
<MoeIcenowy>
well, maybe the only downside is much more expensive price
<MoeIcenowy>
somlo: in fact you can try to revert your change on ~CS, CLK, CKE, ODT pins, and keep DM/DQ/DQS changes
<MoeIcenowy>
and you will get a single-rank 64-bit width setup
<somlo>
yeah, I did *not* tinker with the chip model in the target file, all I did was add the "missing" pins -- like I said, I haven't studied LiteDRAM's internals too closely yet...
<MoeIcenowy>
SODIMMs are by specification 64-bit, although 32-bit SODIMMs exist as unstandard things
<MoeIcenowy>
so I think using 64-bit width should be safe on VC707 unless special SODIMMs are used
<MoeIcenowy>
well I don't know how LiteDRAM perform on ranks too
<MoeIcenowy>
because my STLV7325 is also "dual-rank capable board shipped with single-rank SODIMM"
<MoeIcenowy>
strange, S7DDRPHY module will calculate nranks based on cs_n pin count, so if you add one more pin to it dual rank should be enabled
<MoeIcenowy>
(and if your SODIMM is single rank it WILL fail
<MoeIcenowy>
and enabling both 64-bit width and dual rank should quadruple the memory capacity instead of double it
<MoeIcenowy>
although the main LiteX bone seems to be not ready for big memory
<MoeIcenowy>
(but Rocket can access more memory, not via the main LiteX bus
<MoeIcenowy>
P.S. Sitlinv seems to prefer SODIMMs
<MoeIcenowy>
nearly all their boards have SODIMMs
<MoeIcenowy>
even their Cyclone IV boards have DDR2 SODIMM slots
<MoeIcenowy>
(part of A-E115FB, but no DDR2 PHY is available in LiteDRAM for Altera yet
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