_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<MoeIcenowy> somlo: you never need to get this if you have a VC707
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<cr1901> I wonder how I can get "gigantic FPGA board that has more resources than I can use in a lifetime" for not too much money. Even the largest FPGA board I own- lx45 or 35t- is a medium-small/medium size FPGA
<sensille> a Kintex 7 XC7K325T looks like a good step in that direction
<sensille> from the above mentioned store
<sensille> _florent_: i misread the code, the uart does synchronize to the edge of the start bit and samples in the middle of the bittime, so only filtering could be added
<MoeIcenowy> sensille: QMTECH has some more cheap 7k325t, but I choose Sitlinv one because it has some useful peripherals
<MoeIcenowy> and STLV7325 has GTPs wired out
<MoeIcenowy> QM 325t board just wasted them
<MoeIcenowy> for Sitlinv one you can use LitePCIe, LiteSATA, LiteETH with SFP with GTPs
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<MoeIcenowy> (well to be honest I used none now
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<wild> on the topic of adding support for multiple BARs in litepcie, wouldnt the place to target be the address decoder fed into LitePCIeSlaveInternalPort?
<wild> i know now since testing that other BAR hits will be detected and be translated, I had BAR1 read into a space that BAR0 was mapped to.
<wild> the issue is decoding the incoming address for different regions.
<wild> support for multiple base addresses
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