I wonder how I can get "gigantic FPGA board that has more resources than I can use in a lifetime" for not too much money. Even the largest FPGA board I own- lx45 or 35t- is a medium-small/medium size FPGA
a Kintex 7 XC7K325T looks like a good step in that direction
from the above mentioned store
_florent_: i misread the code, the uart does synchronize to the edge of the start bit and samples in the middle of the bittime, so only filtering could be added
sensille: QMTECH has some more cheap 7k325t, but I choose Sitlinv one because it has some useful peripherals
and STLV7325 has GTPs wired out
QM 325t board just wasted them
for Sitlinv one you can use LitePCIe, LiteSATA, LiteETH with SFP with GTPs
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(well to be honest I used none now
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on the topic of adding support for multiple BARs in litepcie, wouldnt the place to target be the address decoder fed into LitePCIeSlaveInternalPort?
i know now since testing that other BAR hits will be detected and be translated, I had BAR1 read into a space that BAR0 was mapped to.
the issue is decoding the incoming address for different regions.