_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> i might have found it, testing
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<sensille> the tx slots get implemented as LUT RAM :-/
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<sensille> looks like this is an ongoing issue
<sensille> FullMemoryWE makes it even worse, split into 4 memories, each implemented in LUTs
<sensille> the problem seems to be in the R/W wishbone port. when i remove the read capability, it gets inferred correctly. i don't need to read the tx buffer
<sensille> although it might be helpful for generating checksums
<mithro> Some people here might find https://github.com/CAS-Atlantic/parmys-plugin interesting
<sensille> without individual write enables it works with read/write
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