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<sensille>
i might have found it, testing
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<sensille>
the tx slots get implemented as LUT RAM :-/
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<sensille>
looks like this is an ongoing issue
<sensille>
FullMemoryWE makes it even worse, split into 4 memories, each implemented in LUTs
<sensille>
the problem seems to be in the R/W wishbone port. when i remove the read capability, it gets inferred correctly. i don't need to read the tx buffer
<sensille>
although it might be helpful for generating checksums