_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<manawyrm> Hey :) So I'm a bloody, bloody novice in all things HDL, but I'm fiddling around with LiteEth on an ECP5 (Colorlight 5A-75E).
<manawyrm> So far I have a bit of Verilog which tries to accept packets from the ethernet and parse those.
<manawyrm> Using LiteEth "manually" from Verilog is probably not a recommended way of doing things (?), but I wanted to keep things simple.
<manawyrm> Currently accessing the data in 32bit wide blocks (which seems to be a new feature?) and might be less well tested?
<manawyrm> Anyway; I'm struggling to get a reliable end of frame from the LiteEthUDP2StreamRX and I'm wondering if I'm holding it wrong or if that's somehow not working quite right.
<manawyrm> I don't need UDP specifically, just raw Ethernet would also be fine. Is there a good way for me to just get raw, delimited Ethernet frames?
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