<sensille>
is there a naming scheme convention, that everything named litexxx is a library?
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<jevinskie[m]>
<MoeIcenowy> "(part of A-E115FB, but no DDR2..." <- I have their Arria V board and would like to get either full litedram support or at least support using Intel memory controller IP if anybody wants to help :) https://m.aliexpress.us/item/2255801119647489.html
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<jevinskie[m]>
Anybody have a spiffy setup for editing a project on one device then rsycing the project to a build server, building, then rsyncing the results back to the editing machine?
<jevinskie[m]>
If not I’ll try hacking one up using RPyC. I hate having to use a separate (arm64) Mac and Linux machine :P
<tpw_rules>
litex one specifically?
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<wild>
Hi, does anyone know how BARs are mapped internally with litepcie? Trying to map a BAR to a specific region on the device side.
<zyp>
I think by default you're getting one BAR mapped to the CSR region
<wild>
how is that set? via the mmap code in gen.py? Im trying to map an expansion rom bar to a region i have initialised with an option rom.
<wild>
But havent figured out how BARs get assigned to a memory location on the device side. i.e the CSR region. Okay ill look for the CSR region mapping.