07:23 <_florent_> knicklicht: This should be possible yes, you can find some OpenOCD .cfg files in litex_boards, ex this one should be close to what you want to do: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/prog/openocd_trellisboard.cfg

07:27 <knicklicht> Thanks, I will have a look at it. Currently I just use openFPGAloader to load it manually. I finally got everything set up. I also managed to build Zephyr and boot it. Really happy with how nice everything fits together. Next step: Enable I2S cores. It should be possible to have multiple instances of the same core, right?

07:33 <_florent_> knicklicht: Great for Zephyr, what was the issue? (could be useful to know what it was is someone has the same issue in the future)

07:34 <_florent_> knicklicht: The SoC builder will allow you to integrate multiple I2S cores yes, you will just have to see if https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_json2dts_zephyr.py can generate .dts for multiple instances.

07:35 <knicklicht> I just needed to enable the timer uptime latch with: --timer-uptime . This is not mentioned in any tutorials out there as far as I can tell but the Zephyr build error hints at it

07:35 <_florent_> knicklicht: if not, you'll have to edit the script of do manual copy/changes in the .dts.

07:35 <_florent_> knicklicht: after this, zephyr should be able to handle the multiple I2S instances

07:35 <knicklicht> Perfect

07:36 <knicklicht> Ah, a quick search tells me that --timer-uptime was mentioned in the Zephyr guide to get litex vexriscv running on the Arty

07:37 <_florent_> Thanks for the info on the issue

07:37 <_florent_> I just opened https://github.com/enjoy-digital/litex/issues/1555 to have a closer look at it

08:45 <MoeIcenowy> _florent_: BTW as I didn't change OpenC906 for a long time, should we create pythondata-cpu-openc906?

09:57 <knicklicht> Is there a tutorial on how to add a core to a soc? I found an example repo that shows how to add I2S but it's two years and I am unsure if it's up to date: https://github.com/antmicro/zephyr-on-litex-vexriscv/blob/0775f94d3537ec5e967ea2ac2b6aba0de3fa71af/soc_zephyr.py

11:12 <knicklicht> When I try to build I get "i2s_tx Region in IO region, it can't be cached: Origin: 0xb2000000, Size: 0x00040000, Mode: RW, Cached: True Linker: False" caused by: self.add_memory_region("i2s_tx", 0xb2000000, i2s_mem_size). In the example the memory regions are allocated differently. Where can I find out how to do the mapping?

11:42 <knicklicht> Okay, I bypassed that by setting the region adress to something before ethmacs bus range. Now I have a more serious problem, the i2s core seems to be designed only for xilinx devices. It directly uses  FIFOSyncMacro from litex.soc.cores.ram.xilinx_fifo_sync_macro. Is there an alternative for the ECP5?

22:04 <_florent_> MoeIcenowy: We should create a pythondata-cpu-openc906 repo yes, I could look at it next week