<DerekKozel[m]>
Actually bringing up the AD9364 RF frontend would be a bunch of work (I assume), though nothing new for LiteX as there are already designs using the same RFIC
<gurki>
ah. i cant help with litex stuff, i just happen to own and use a pluto
<knicklicht>
Hey, can someone tell me why I get timing issues when I try to build ./litex_boards/targets/colorlight_5a_75x.py --cpu-type vexriscv --with-ethernet --csr-json csr.json --build. I get the following warnings:
<knicklicht>
Warning: Max frequency for clock '$glbnet$crg_clkout0': 59.92 MHz (FAIL at 60.00 MHz)
<knicklicht>
Warning: Max frequency for clock '$glbnet$eth_clocks0_rx$TRELLIS_IO_IN': 112.76 MHz (FAIL at 125.00 MHz)
<knicklicht>
The closed github issues seem to indicate, that liteeth should work on ECP5 FPGAs.
<sensille>
knicklicht: i had better success with yosys from oss-cad-suite-20220407
<sensille>
but you have to experiment with some tuning. timing closure is possible, but it also failed for me out of the box
<knicklicht>
Thanks, I will try the alternative version of yosys. How do I go about tuning the core?
<sensille>
i just tried some recommended yosys setting. not sure if i can still find them
<sensille>
one thing to try is "scratchpad -copy abc9.script.flow3 abc9.script; synth_ecp5 -abc9"
<sensille>
or just "synth_ecp5 -abc"
<sensille>
*abc9
<knicklicht>
Okay, I will have to get familiar with yosys first. I wouldn't know where to set this
<knicklicht>
is it correct that I use --with-ethernet and not --with-etherbone?
<sensille>
depends on what you want to achieve. shouldn't have an impact on the 120mhz timing
<sensille>
regarding the 60mhz you might also just reduce the target to 50mhz
<knicklicht>
I want to run zephyr on the vexriscv
<sensille>
--with-ethernet means you do ip in software, to whatever extent
<sensille>
--with-etherbone means ethernet is handled autonomously by gateware and you only map memory regions which you can access over network
<knicklicht>
Okay, so for my use case --with-ethernet makes sense
<sensille>
i guess you can run zephyr in both variants, but i have no experience with zephyr
<knicklicht>
Okay, thanks that helped anyways. The oss-cad-suite build got 60.47 MHz out of the box. I now only need to figure out how to get from 97.26 Mhz to 125MHz
<sensille>
that's the more important part
<knicklicht>
Where do I set the "scratchpad synth_ecp5 -abc"?
<sensille>
for a test you can manually edit colorlite.ys
<knicklicht>
Which I can find where? Sorry, I am absolutely new to Lattice FPGAs
<sensille>
build/gateware/
<sensille>
it is automatically generated
<knicklicht>
So I need to interrupt the build process right after the file is generated? If I just rebuild with the "-abc9" added, the file is just overwritten
<sensille>
i think after the build is done, you can go to build/gateware, change colorlite.ys and call build_colorlite.sh
<sensille>
knicklicht: 123.46 MHz (FAIL at 125.00 MHz). close ...
<knicklicht>
You are my personal hero:-) .That worked. I now have 126Mhz. The clock is at 55.96Mhz, I'll just set the clock to 50MHz
<sensille>
\o/
<sensille>
remember that yosys uses a random seed, so results may vary from run to run
<knicklicht>
I saw that. Maybe I'll rerun a few times until I get 60MHz