01:46 <Guest63> After some digging, I believe I am experiencing issues

01:46 <Guest63> similar to this one:

01:46 <Guest63> https://github.com/enjoy-digital/litex/issues/831

03:20 <Guest63> After adding the following command     VerilatedVcd::flush_all();  to litex_sim_dump()  in sim_init.cpp

03:20 <Guest63> and rebuilding and rerunning

03:21 <Guest63> my VCD dump now finishes the definitions

03:21 <Guest63>      $var wire 1 G^" when_InstructionCache_l459_2 $end

03:21 <Guest63>      $var wire 1 7x# when_Utils_l357 $end

03:21 <Guest63>     $upscope $end

03:21 <Guest63>    $upscope $end

03:21 <Guest63>   $upscope $end

03:21 <Guest63>  $upscope $end

03:21 <Guest63> $enddefinitions $end

03:21 <Guest63> however, there are still no traces

05:05 <Guest63> Going on an even deeper dive, it appears that :

05:06 <Guest63> g_sim->sim_trace in veril.cpp is never set true

05:06 <Guest63> when the LPDDR4 simulations are built

05:06 <Guest63> i am not too sure what this represents exactly, but it appears that this should be set to be true

06:51 <_florent_> subthreshold: Great that you manage to export the simulation model. To avoid exposing dq_o, dq_i, dq_oe, you could use a Tristate, similar to: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1658

06:52 <_florent_> subthreshold: For the dump issue, make sure you have this in your sim: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L288

07:07 <Guest63> Hi Florent, hope you had a great weekend for the help on this again! Yes I think adding trace to self.comb fixed it (looks like the dump is generating properly now). Re-examining simsoc.py, I realize now that it only has platform.add_debug(self, reset=trace_reset) and not the trace command.

07:16 <_florent_> Guest63: Thanks yes. I had the issue recently, we should really set the default value to 1 when the signal is not driven to avoid this. I just created https://github.com/enjoy-digital/litex/issues/1269 for this.

07:29 <Guest63> Hi Florent, I actually realized that adding that the reason why it was dumping was because of a hack I made earlier when trying things. I've rolled everything back, with the only change being that I commented line 86 from simsoc.py out and added instead self.comb += platform.trace.eq(1).

07:31 <Guest63> Running this command: python litedram/phy/lpddr4/simsoc.py --log-level info --finish-after-memtest --double-rate-phy --l2-size 0 --trace --trace-fst --gtkw-savefile

07:32 <Guest63> it's still generating empty dumps.

07:37 <_florent_> subthreshold: I'll have a closer look this week, what was the hack you did?

07:38 <_florent_> (Maybe you can keep it for now until I have a closer look)

07:45 <subthreshold> Oh, this looks like an error on my side. Seems like my editor desynced and I was running old code. Adding the command you suggested seems to be working. Will let this sim run overnight and look at the fst tmrw.

07:46 <subthreshold> Thanks again!

16:09 <davebee> Is there a build flag that is only set when building the BIOS? I'm trying to share a library between the BIOS and the application code. I just want some conditional compilation when building the BIOS, but not the app.

17:37 <somlo_> booting Linux on LiteX+Rocket over SATA: https://pastebin.com/p4ZM4iLx

17:37 <tpb> Title: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ - - Pastebin.com (at pastebin.com)

17:38 <somlo_> _florent_: the one caveat is that one currently MUST power-cycle the SATA drive after programming bitstream into the nexys_video board, otherwise reading from the drive will hang the LiteSATA gateware

20:18 <_florent_> somlo: good, that's already some progress with your setup :)

20:19 <_florent_> somlo: what's the model of your SSD? I could try to buy one to reproduce the issue

20:59 <somlo> _florent_: it's an `MZ-77E250B/AM`