_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 268 seconds]
Degi_ is now known as Degi
Dustin has joined #litex
Dustin has left #litex [#litex]
LoveMHz has joined #litex
LoveMHz_ has joined #litex
LoveMHz has quit [Quit: Client closed]
LoveMHz_ is now known as LoveMHz
subthreshold has quit [Quit: Client closed]
_franck_ has quit [Quit: Ping timeout (120 seconds)]
_franck_ has joined #litex
Guest63 has joined #litex
Guest63 has quit [Quit: Client closed]
geertu has joined #litex
Guest49 has joined #litex
Guest49 has quit [Quit: Client closed]
MoeIcenowy has quit [Quit: ZNC 1.7.2+deb3 - https://znc.in]
MoeIcenowy has joined #litex
_franck_ has quit [Quit: Ping timeout (120 seconds)]
_franck_ has joined #litex
zjason` has joined #litex
zjason has quit [Ping timeout: 260 seconds]
subthreshold has joined #litex
geertu has quit [Ping timeout: 268 seconds]
Guest63 has joined #litex
<Guest63> Has anyone ever run into issues with the trace dump?
<Guest63> I have been running the following command:  python litedram/phy/lpddr4/simsoc.py --log-level info --finish-after-memtest --trace --gtkw-savefile
<Guest63> I have pyvcd 0.3.0 installed, and it's currently running through the sim and creating a vcd.
<Guest63> However, examining the vcd, I noticed that it has no time stamps, which is leading to gtkwave not being able to initialize the vcd dump
<Guest63> To clarify: not no timestamps but no signals in general*
<Guest63> The exact error being: No symbols in VCD file..is it malformed? Exiting!
geertu has joined #litex