06:29 <tnt> _florent_: so turns out that the workaround I used to get sys_clk above doesn't work ...

06:29 <tnt> it results in multiple `wire` in the generated verilog, each of them with the don_touch attribute set ... forcing vivado to create multiple clock networks, each skewed with each other.

07:00 <tnt> mmmm ... maybe I was a little quick to jump to the conclusion that this was the issue. yet TBD

07:47 <tnt> Nope nevermind, it was the issue.

14:09 <_florent_> tnt: I imagine you are trying to apply a constraint internally in a submodule/peripherals of the SoC. What you could also do is add a "add_timing_constraint" method to your module and call it from the SoC

14:09 <_florent_> tnt: similar to this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/dna.py#L43-L45

20:37 <tnt> _florent_: yeah, I ended up just passing the sys_clk signal to the constructor directly.

20:38 <tnt> I'm having trouble bringing the JESD link up for some reason. It was working a couple month back, haven't tried it since and ... not sure what I'm screwing up now.