_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<subthreshold> Hi _florent_, I was wondering, for the LiteDRAM unit tests, like test_bandwidth
<subthreshold> can I dump waveforms somehow
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<Guest89> Is there a way to connect an external CPU to LiteX cores via 8bit parallel bus?
<Guest89> Can I use csr_bus for this?
<Guest89> Or would emif be the right direction?
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<_florent_> subthreshold: you can add vcd_name="sim.vcd" to run_simulation to dump the waveforms
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