_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<DerekKozel[m]> florent: Has there been anything new about the accelerator concept?
<_florent_> DerekKozel[m]: Not directly on the concept but indirectly on the cores/components yes.
<_florent_> DerekKozel[m]: There is also https://github.com/enjoy-digital/xtrx_julia that could be interested where we are progressively re-creating a gateware for the XTRX
<_florent_> DerekKozel[m]: P2PDMA has also been tested with LitePCIe to transfer samples directly from/to GPUs and do the processing there
<_florent_> DerekKozel[m]: And I added 64-bit support to LitePCIe DMA for this (but only for 64-bit data-paths for now, so up to PCIe Gen2 X2)
<DerekKozel[m]> Ok. I talked with the Julia folks at the start of the year and they have a talk at FOSDEM.
<DerekKozel[m]> I was thinking of picking up the CLE-215 again this weekend and updating the LitePCIe interface in GNU Radio to the latest on both sides
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<shorne> yay, I think I fixed the mor1kx dcache bug
<shorne> It took about a month to rewrite the formal verification to the point where 1. I could understand the workings of the load-store-unit enough and 2. I could use the formal verification to reproduce the dcache bug
<shorne> after that the fix was trivial, but having the formal verification + other regression testing in place to be able to give me confidence the fix is not introducing bugs was the key
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