_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Melkhior> hello ; is 'make.py' in linux-on-litex-vexriscv still supported ? It seems to be broken right now, csr and irq and region (and maybe more) are added twice, by such commit as e6e3a909f and 3b4a88536
<Melkhior> e.g. "./make.py --board=arty_a7" --build fails instantly complaining about uart csr being added twice
<_florent_> Hi Melkhior, it should yes. I've moved the specific things to LiteX (to also allow building Linux-on-LiteX-VexRiscv SoC directly from LiteX-Boards when using --cpu-type=vexriscv-smp)
<_florent_> but I'm going to check
<Melkhior> @_florent_: commenting the 5 offending lines in cpu/vexriscv_smp/core.py (2 csr, 2 irq, 1 region) seem to work around the issue for me...
<_florent_> are you using a linux-on-litex-vexriscv fork?
<_florent_> if so, make sure to apply:
<_florent_> Melkhior: it builds fine here with up to date LiteX/Linux-on-LiteX-VexRiscv
<Melkhior> @_florent_ no it should be a clean Litex install just updated by the script
<Melkhior> ... but maybe I didn't explicitly update linux-on-litex-vexriscv :-/ silly me
<Melkhior> indeed with an update linux-on-litex-vexriscv it seems OK
<_florent_> Melkhior: Good, in fact linux-on-litex-vexriscv is now mostly build/use instructions for the gateware/buildroot and pre-configured targets. All the real contents has moved to LiteX or LiteX-Boards.
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