_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<zyp> it's making my build fail with ValueError: Multiple submodules with local clock domains cannot be anonymous
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<AndrewD> tnt: thanks, I assumed there must be a reason for the pattern but using litex is my first reason to take python seriously. I've discovered I quite like it!
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<_florent_> zyp: ok, I'll see if I can do this differently
<tnt> _florent_: btw, tried again with updated litex/litepci still same issue in x8 :/
<tnt> So I if you have the litescope code to probe the inside, I can try that next.
<_florent_> tnt: Thanks, you could use this:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> and trigger on m_axis_rc.valid before starting the dma_test
<_florent_> to see if you the DMA Reader receives the first completions. And once stuck, if you can do another capture to see if that's rc channel that is stuck (valid=1, ready=0)
<tnt> Ack.
<_florent_> zyp: not very clean, but this should fix your build. I'll probably have another look at it.
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<Melkhior> hello; what would be the 'recommended' way to clear (set all words to 0) a Memory() object? I find myself in need of clearing the tag memory of a wishbone cache to "flush" it but not sure how to do that (no lines need eviction as I converted it from write-back to write-through/write-no-allocate)
<Melkhior> thanks
<Melkhior> (I tried a ResetInserter() but those don't seem to work on Memory ?)
<_florent_> tnt: ok, thanks. So it seems to start correctly and nothing indicates that a channel is blocked when it's hanging.
<_florent_> tnt: it would be interesting to add these signals:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> Melkhior: A Block RAM does not have a reset pin, you'll have to implement your own logic to do clear the sections you want
<_florent_> Melkhior: You could share one of the port of the Memory for this, or add another specific. But if you already have 2 ports, adding another will prevent the use of BlockRAM.
<Melkhior> @_florent_ OK thanks! it should only have one port (it's basically the tag_mem from the wishbone cache) so I could add a loop to reset all tag bits to zero
<Melkhior> (or I could try and do some snooping to only invalidates lines that have been write-touched by the host... but that's probably harder)
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